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首页> 外文期刊>Japanese Journal of Applied Physics. Part 1, Regular Papers, Brief Communications & Review Papers >Hot-Carrier Degradation and Electric Field and Electron Concentration near Drain Junction in Low-Temperature N-Channel Single Drain and Lightly Doped Drain Polycrystalline Silicon Thin Film Transistors
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Hot-Carrier Degradation and Electric Field and Electron Concentration near Drain Junction in Low-Temperature N-Channel Single Drain and Lightly Doped Drain Polycrystalline Silicon Thin Film Transistors

机译：低温N沟道单漏极和轻掺杂漏极多晶硅薄膜晶体管的漏极结附近的热载流子降解以及电场和电子浓度

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摘要

We proposed a two-dimensional (2-D) physical model of n-channel polycrystalline silicon (poly-Si) single drain (SD) and lightly-doped drain (LDD) thin film transistor (TFT) to analyze hot-carrier degradation. The model is based on a 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. It is found that, for current saturation bias, the maximum 2-D lateral electric field is located in the deep drain region under the gate, and the current flows in the deep channel region near the drain junction. In poly-Si n-channel TFTs, it was predicted from our 2-D device simulation that the generation of both band-tail states in poly-Si and interface states at both interfaces can contribute to hot-carrier degradation. We have shown that, in the case of n-channel SD TFTs, generated band-tail states greatly affect drain avalanche hot-carrier (DAHC) degradation for longer stress time of 10,000s.
机译：我们提出了n沟道多晶硅（poly-Si）单漏极（SD）和轻掺杂漏极（LDD）薄膜晶体管（TFT）的二维（2-D）物理模型，以分析热载流子退化。该模型基于2D器件模拟器的高斯掺杂分布图，该分布图适用于从2D过程模拟器获得的多晶硅中的横向和纵向杂质分布拟合的源极和漏极结。发现，对于电流饱和偏置，最大的二维横向电场位于栅极下方的深漏极区域中，并且电流在漏极结附近的深沟道区域中流动。在多晶硅n沟道TFT中，根据我们的2-D器件仿真预测，多晶硅中两个带尾态的产生以及两个界面处的界面态的产生都可能导致热载流子退化。我们已经表明，在n通道SD TFT的情况下，所产生的带尾状态在较长的10,000s应力时间内会严重影响漏极雪崩热载流子（DAHC）的退化。

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