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首页> 外文期刊>Japanese journal of applied physics >Full-Chip Lithography Verification for Multilayer Structure in Electron-Beam Lithography
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Full-Chip Lithography Verification for Multilayer Structure in Electron-Beam Lithography

机译：电子束光刻多层结构的全芯片光刻验证

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摘要

In this study, a simplified electron energy flux (SEEF) model for electron-beam (EB) lithography has been evaluated by comparing it with the Monte Carlo (MC) simulation for copper (Cu) wiring layers. The parameters of the SEEF model in each layer depend not only on the density and thickness of the material but also on the depth of the material in the substrate. Moreover, as the number of underlying layers including metals increases, the number of parameters of the SEEF model increases; thus, the difficulty in parameter extraction markedly increases. We have attempted to extract the optimum parameters of the SEEF model in each layer using the MC simulation. As a result, it was found that the differences in the backscattered electron energy fluxes from several layers with different combinations of Cu densities between the SEEF model and the MC simulation were within a range from -1.56 to +0.74%.
机译：在这项研究中，通过将其与铜（Cu）布线层的蒙特卡洛（MC）仿真进行比较，评估了用于电子束（EB）光刻的简化电子能量通量（SEEF）模型。每层SEEF模型的参数不仅取决于材料的密度和厚度，还取决于基材中材料的深度。此外，随着包括金属在内的基础层的数量增加，SEEF模型的参数数量也随之增加。因此，参数提取的难度显着增加。我们尝试使用MC仿真提取每层SEEF模型的最佳参数。结果，发现在SEEF模型和MC模拟之间来自具有Cu密度的不同组合的几层的反向散射电子能通量的差异在-1.56％至+ 0.74％的范围内。

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