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首页> 外文期刊>Japanese Journal of Applied Physics. Part 1, Regular Papers & Short Notes >Dependence of Time-Dependent Dielectric Breakdown Lifetime on the Structure in Cu Metallization
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Dependence of Time-Dependent Dielectric Breakdown Lifetime on the Structure in Cu Metallization

机译：随时间变化的介电击穿寿命与铜金属化过程中结构的关系

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摘要

Time-dependent dielectric breakdown (TDDB) in Cu metallization and its dependence on the presence of a barrier metal, the kind of barrier metal, barrier metal thickness, the low-k dielectric and the low-k barrier dielectric, is investigated. There is a distinct difference between TDDB degradation mechanisms with and without barrier metals. The degradation mechanism is drift through the bulk without the barrier, but drift along the CMP surface with the barrier. The barrier property against TDDB is better for Ta and TaN than that for TiN. The TDDB characteristic is independent of the barrier metal thickness, but depends strongly on the electric field strength in the structure. The degradations, related to Cu ion diffusion, are mainly caused by electrical stress, not thermal stress. In a low-k structure, the leakage current path is along the CMP surface due to the electric field concentration. The TDDB lifetime with a barrier metal depends on the breakdown voltage of the low-k material. The TDDB lifetime decreases as the k-value becomes lower. Although the use of low-k barrier dielectrics decreases the TDDB lifetime, a satisfactory TDDB lifetime is achievable with a low-k barrier dielectric as thin as 25 nm. All low-k structures in our study satisfy the 10-year projected TDDB reliability. However, the TDDB lifetime for technology generations beyond the 65nm-node CMOS may have inadequate 10-year reliability.
机译：研究了铜金属化过程中随时间变化的介电击穿（TDDB）及其与阻挡金属，阻挡金属的种类，阻挡金属厚度，低k介电常数和低k阻挡介电常数的关系。有和没有势垒金属的TDDB降解机制之间都有明显的区别。降解机理是在没有阻挡层的情况下漂移通过主体，而在具有阻挡层的情况下沿着CMP表面漂移。 Ta和TaN对TDDB的阻挡性能比TiN更好。 TDDB特性与势垒金属厚度无关，但在很大程度上取决于结构中的电场强度。与铜离子扩散有关的降解主要是由电应力而不是热应力引起的。在低k结构中，由于电场集中，泄漏电流路径沿着CMP表面。势垒金属的TDDB寿命取决于低k材料的击穿电压。 TDDB的寿命随着k值的降低而降低。尽管使用低k势垒电介质会降低TDDB寿命，但使用低至25 nm的低k势垒电介质仍可实现令人满意的TDDB寿命。我们研究中的所有低k结构都满足TDDB十年可靠性预测。但是，TDDB在超过65nm节点CMOS的技术世代的使用寿命可能不足10年可靠性。

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