Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

Bipul C. Paul; Kaushik Roy

首页> 外文期刊>Journal of Electronic Testing >Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

【24h】

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

机译：体偏置对100nm以下CMOS电路延迟故障测试的影响

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology generations [11, 12]. It is shown that forward body bias (FBB) reduces the leakage power and suppresses the effect of process variation while reducing the complexity of dualVth technology. In this paper, we study the effect of body bias on the delay fault testing of CMOS circuits. We analyze the impact of both fixed and adaptive body biasing techniques on test cost and the quality of test. Statistical analysis on several benchmark circuits shows that the adaptive body biasing design will have the most effective impact on delay fault by maintaining the test cost at its minimum under process variation while ensuring the test quality at its highest level.

机译：最近，有人提出了一种用于100纳米以下技术的微处理器的体偏置技术[11，12]。结果表明，前向体偏置（FBB）在降低DualVth技术的复杂性的同时，降低了泄漏功率并抑制了工艺变化的影响。在本文中，我们研究了体偏置对CMOS电路延迟故障测试的影响。我们分析了固定的和自适应的身体偏置技术对测试成本和测试质量的影响。对几个基准电路的统计分析表明，自适应本体偏置设计将通过在过程变化下将测试成本保持在最低水平，同时确保测试质量处于最高水平，从而对延迟故障产生最有效的影响。

著录项

来源
《Journal of Electronic Testing》 |2006年第2期|115-124|共10页
作者
Bipul C. Paul; Kaushik Roy;
展开▼
作者单位

Toshiba America Research Inc.;

School of Electrical and Computer Engineering Purdue University;

展开▼
收录信息
原文格式 PDF
正文语种 eng
中图分类
关键词
delay fault testing; adaptive body bias design; process variation; statistical analysis;

机译：延迟故障测试;自适应偏置设计;过程变化;统计分析;

相似文献

外文文献
中文文献
专利

1. Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits [J] . BIPUL C. PAUL, KAUSHIK ROY Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2006,第2期

机译：体偏置对100 nm以下CMOS电路延迟故障测试的影响
2. Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits [J] . Pomeranz I., Reddy S. M. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2011,第2期

机译：在标准扫描电路中测试路径延迟故障所需的输入必要分配
3. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology [J] . Chatterjee B., Sachdev M. IEEE transactions on very large scale integration (VLSI) systems . 2005,第11期

机译：采用180nm CMOS技术的1.7GHz低功耗可延迟故障测试的32b ALU的设计
4. Impact of body bias on delay fault testing of nanoscale CMOS circuits [C] . Paul B.C., Neau C., Roy K. Test Conference, 2004. Proceedings. ITC 2004 . 2004

机译：体偏置对纳米级CMOS电路延迟故障测试的影响
5. Test generation and evaluation for bridging faults in CMOS VLSI circuits. [D] . Lee, Terry Ping-Chung. 1995

机译：测试生成和评估CMOS VLSI电路中的桥接故障。
6. Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits [O] . Yiming Li, Chieh-Yang Chen, Min-Hui Chuang, 2019

机译：随机纳米氮化钛晶粒引起的动态功率延迟的特性波动以及全能门纳米线CMOS器件和电路的纵横比效应
7. Circuit Engineering Modeling of Single Event Effects under Impact of Heavy-Charged Particles in SUB-100 NM CMOS ICs [O] . A.A. Smolin, A.B. Boruzdina, A.V. Ulanova, 2017

机译：单次事件效应的电路工程建模在亚100nmCMOS IC中的大带粒子冲击下的影响

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

摘要

著录项

相似文献

相关主题

期刊订阅