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首页> 外文期刊>Journal of Electronic Testing >Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
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Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

机译：具有多个故障的扫描设计的精确全芯片诊断策略

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摘要

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults.
机译：全扫描设计的故障诊断已取得显着进展。但是，大多数现有技术都针对具有单个故障的逻辑块。为了成功诊断出具有多个故障的大型芯片，需要采用这些块级技术之上的策略。在本文中，我们提出了这样一种策略。我们的策略可有效地准确识别多个故障。它分两个阶段进行。在第一阶段，我们专注于基于称为词级主要候选项的概念对所谓的结构独立故障的识别，而在第二阶段，我们进一步跟踪更难以捉摸的与结构相关的故障的位置。实验结果表明，该策略能够在随机注入5个节点型故障或卡死故障的三种实际设计中，在10次信号检查中发现3至4个故障。

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