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首页> 外文期刊>Journal of The Institution of Engineers (India): Series B >High-Speed High-Throughput VLSI Architecture for RSA Montgomery Modular Multiplication with Efficient Format Conversion
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High-Speed High-Throughput VLSI Architecture for RSA Montgomery Modular Multiplication with Efficient Format Conversion

机译:用于高效格式转换的RSA Montgomery模块化乘法的高速高通量VLSI架构

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Modular multiplication is a key operation in RSA cryptosystems. Modular multipliers can be realized using Montgomery algorithm. Montgomery algorithm employing carry save adders makes modular multiplication suitable and efficient. Montgomery modular multiplication can be carried out in two ways. All the operands are kept in carry save form in one of the ways. The input and output are kept in binary form, and intermediate operands are kept in carry save form in the other way which requires an efficient format converter. This paper proposes a fast and high-throughput Montgomery modular multiplier which employs an efficient format conversion method. Format conversion is carried out through a format conversion unit which consists of a carry look-ahead unit and multiplexer unit. In addition, this multiplier merges two iterations, which reduces the number of clock cycles significantly. Merger of iteration requires integer multiples of inputs which is computed using the same format converter. Critical path delay of the multiplier is minimized by multiplying one of the inputs by four which simplifies necessary intermediate calculations. The total time required for one complete multiplication is significantly minimized due to reduction in required number of clock cycles with optimum critical path delay. Experimental results show that the proposed multiplier achieves significant speed and throughput improvement as compared to previous designs.
机译:模块化乘法是RSA密码系统中的关键操作。可以使用蒙哥马利算法实现模乘。采用进位保存加法器的蒙哥马利算法使模乘合适且有效。蒙哥马利模乘可通过两种方式进行。所有操作数均以一种方式保留进位保存形式。输入和输出以二进制形式保存,而中间操作数以另一种需要有效格式转换器的方式保存为进位保存形式。本文提出了一种采用高效格式转换方法的快速,高吞吐量的蒙哥马利模乘器。格式转换通过格式转换单元执行,该格式转换单元由进位超前单元和多路复用器单元组成。此外,该乘法器合并了两个迭代,从而显着减少了时钟周期数。迭代合并需要使用相同格式转换器计算的输入整数倍。通过将输入之一乘以四,可以使乘法器的关键路径延迟最小化,从而简化了必要的中间计算。一次完整乘法所需的总时间由于具有最佳关键路径延迟的所需时钟周期数的减少而大大减少。实验结果表明,与以前的设计相比,所提出的乘法器可以显着提高速度和吞吐量。

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