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Enhancing interface quality by gate dielectric deposition on a nitrogen-conditioned 4H-SiC surface

机译:通过在经过氮气处理的4H-SiC表面上进行栅极电介质沉积来提高界面质量

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摘要

Using metal-oxide-semiconductor devices, we show that the density of interface states at the SiO_2/4H-SiC interface can be reduced by applying a N_2 heat treatment to a silicon carbide (SiC) surface prior to the deposition of a gate dielectric. Remarkably, this technique yields an interface that is at least as good as the one formed by thermal oxidation in terms of electrically active defects. This improvement can be traced to nitrogen insertion at the semiconductor surface, which provides a seed layer for subsequent deposition. The nature of N incorporation and its impact on electrical properties were studied using x-ray photoelectron spectroscopy, secondary ion mass spectroscopy, and capacitance-voltage measurements. These results offer a new perspective in the quest to maximize minority carrier mobility and minimize energy loss in 4H-SiC switches.
机译:使用金属氧化物半导体器件,我们显示出可以通过在沉积栅极电介质之前对碳化硅(SiC)表面进行N_2热处理来降低SiO_2 / 4H-SiC界面处的界面态密度。明显地,就电活性缺陷而言,该技术产生的界面至少与通过热氧化形成的界面一样好。这种改进可以追溯到氮在半导体表面的插入,这为随后的沉积提供了种子层。使用X射线光电子能谱,二次离子质谱和电容电压测量研究了N掺入的性质及其对电性能的影响。这些结果为寻求最大化少数载流子迁移率并最小化4H-SiC开关的能量损耗提供了新的视角。

著录项

  • 来源
    《Journal of Materials Research》 |2013年第1期|28-32|共5页
  • 作者单位

    Materials Science Research Laboratory, Central Research Institute of Electric Power Industry, Yokosuka, Kanagawa 240-0196, Japan,IBM T. J. Watson Research Center, Yorktown Heights, NY 10598;

    Materials Science Research Laboratory, Central Research Institute of Electric Power Industry, Yokosuka, Kanagawa 240-0196, Japan;

    Materials Science Research Laboratory, Central Research Institute of Electric Power Industry, Yokosuka, Kanagawa 240-0196, Japan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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