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首页> 外文期刊>Journal of Vacuum Science & Technology >Localized dry-etch substrate thinning for dislocation reduction in heteroepitaxial CdTe/Si(211)
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Localized dry-etch substrate thinning for dislocation reduction in heteroepitaxial CdTe/Si(211)

机译：局部干法蚀刻衬底减薄以减少异质外延CdTe / Si（211）中的位错

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摘要

Threading dislocations are a significant problem for heteroepitaxial growth of thin films on large lattice-mismatched substrates. In the case of HgCdTe thin films on Si, Ge, or GaAs, the molecular beam epitaxy (MBE) of 10-15-μm-thick CdTe buffer layers has historically played a crucial role in reducing threading dislocation densities to current state-of-the-art levels. In this work, the authors investigate a localized substrate thinning approach and its overall effect on further reducing dislocation densities in the CdTe/Si heteroepitaxial system. In using substrates with regions thinned to thicknesses on the order of the CdTe buffer, the attempt is to reduce the dislocation image force acting from the interface toward the epilayer surface. The authors employ both wet- and dry-etching techniques to create locally back-thinned regions of Si(211) wafers. Localized rather than whole wafer thinning was necessary to maintain sufficient substrate thickness for handling. The opposite sides of the wafers were cleaned using standard techniques prior to CdTe MBE. Scanning electron microscopy and Fourier transform infrared spectroscopy were used to measure epilayer and substrate thicknesses. Using CdTe defect-decoration techniques, a decrease in threading dislocation density by up to 60% has been observed in regions for which the underlying Si substrate was thinned to 2 μm. Results obtained for wet-etch and dry-etch back-thinning approaches suggest that the dislocation-reduction mechanism is not solely based on substrate-thickness induced image forces.
机译：对于大晶格不匹配的衬底上的薄膜的异质外延生长，螺纹位错是一个重要的问题。就Si，Ge或GaAs上的HgCdTe薄膜而言，厚度为10-15μm的CdTe缓冲层的分子束外延（MBE）过去一直在将螺纹位错密度降低到目前的状态中起着至关重要的作用。最先进的水平。在这项工作中，作者研究了局部衬底减薄方法及其对进一步降低CdTe / Si异质外延系统中位错密度的总体影响。在使用区域变薄至CdTe缓冲层数量级的基板时，尝试减小从界面向外延层表面作用的位错图像力。作者采用湿法蚀刻和干法蚀刻技术来创建Si（211）晶圆的局部背面减薄区域。为了保持足够的基板厚度以进行处理，必须进行局部减薄而不是整个晶圆变薄。在使用CdTe MBE之前，使用标准技术清洁了晶圆的相对侧。扫描电子显微镜和傅立叶变换红外光谱法用于测量外延层和基底的厚度。使用CdTe缺陷修饰技术，在下面的Si基板变薄至2μm的区域中，观察到了螺纹位错密度降低了60％。通过湿法刻蚀和干法刻蚀减薄方法获得的结果表明，位错减少机制不仅仅基于基板厚度引起的像力。

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  • 来源
    《Journal of Vacuum Science & Technology》 |2011年第3期|p.03C105.1-03C105.6|共6页
  • 作者

    R. N. Jacobs; J. K. Markunas; C. Nozaki; M. Jaime-Vasquez; P. J. Smith; J. D. Benson; J. Pellegrino;

  • 作者单位

    U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate, Fort Belvoir, Virginia 22060;

    U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate, Fort Belvoir, Virginia 22060;

    U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate, Fort Belvoir, Virginia 22060;

    U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate, Fort Belvoir, Virginia 22060;

    U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate, Fort Belvoir, Virginia 22060;

    U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate, Fort Belvoir, Virginia 22060;

    U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate, Fort Belvoir, Virginia 22060;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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