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Strain engineering in SOI-type materials for future technologies

机译：SOI型材料的应变工程用于未来技术

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摘要

Silicon-on-insulator (SOI) is today the substrate of choice for several applications, including high performance and low power ICs. In order to boost further circuit performance, new solutions are being explored. In particular, increasing the charge carrier mobility has been identified as a requirement to meet the performance needs of the 65 nm technology nodes and beyond. One possible option is to increase transistor channel mobility through local strain engineering via stressors like nitride layers or epitaxial SiGe source/drain pockets. This is the so-called "local strain" or "process-induced strain" approach. Another solution is to induce a MOSFET mobility increase via substrate engineering, which presents the advantage of being independent of transistor geometry. If necessary, the two approaches can be combined. The attractiveness of wafer level-based solutions is largely due to their compatibility with standard CMOS integration processes and architectures. Among the different substrate level options investigated by the industry, we will focus here on strained Si layers on insulator. Different wafer manufacturing techniques will be considered, and the potential of wafer bonding and layer transfer techniques will be highlighted.
机译：如今，绝缘体上硅（SOI）已成为包括高性能和低功耗IC在内的多种应用的首选衬底。为了进一步提高电路性能，正在探索新的解决方案。特别地，已经确定增加电荷载流子迁移率是满足65 nm技术节点及以后的性能需求的要求。一种可能的选择是通过局部应变工程，通过诸如氮化物层或外延SiGe源/漏袋的应力源，来提高晶体管的沟道迁移率。这就是所谓的“局部应变”或“过程引起的应变”方法。另一解决方案是通过衬底工程来引起MOSFET迁移率的增加，这具有独立于晶体管几何形状的优点。如有必要，可以将这两种方法结合起来。基于晶圆级解决方案的吸引力很大程度上归功于它们与标准CMOS集成工艺和体系结构的兼容性。在业界研究的不同衬底级别的选择中，我们将重点关注绝缘体上的应变Si层。将考虑不同的晶圆制造技术，并将重点介绍晶圆键合和层转移技术的潜力。

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