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Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

机译:具有模版沉积金属栅极的双极性硅纳米线FET

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We report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si) and SiO_2 layers as well as metal gate patterning using stencil lithography, demonstrated for the first time. FinFETs with stenciled Al gates are successfully co-fabricated with polycrystalline silicon O-gated devices. Stencil lithography is envisaged as a key enabler for gate patterning on 3D structures, such as vertically stacked nanowire transistors.
机译:我们报告了一种用于双极性硅纳米线FinFET的完全CMOS兼容的制造方法。低热预算处理,与单片3D器件集成兼容,利用了非晶硅(a-Si)和SiO_2层的低压化学气相沉积(LPCVD)以及使用模板光刻的金属栅极图案化,这是首次展示。具有模板铝栅极的FinFET已成功与多晶硅O型栅极器件共同制造。模版光刻被设想为在3D结构(例如垂直堆叠的纳米线晶体管)上进行栅极构图的关键因素。

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