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Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic

机译：定制和自动布线修复工具集，可抵抗侧通道分析的双轨逻辑

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摘要

Dual-rail Precharge Logic (DPL) has been widely studied as an effective countermeasure category for mitigating Side Channel Attack (SCA) threats, where unwanted physical leakages from running crypto devices are inspected and analyzed to retrieve confidential data. DPL protocol requires compensated behavior between the corresponding rails, which differs from conventional logic principles. Thus it needs unusual design flows with repetitive and tedious workload. In this article, we present a custom execution tool to automatically realize a dual rail logic. This controllable and automated design flow relies on Xilinx FPGA platforms, to obtain dual rails with highly symmetric networks. The tool is able to automate the logic transformation from a raw single rail on Xilinx Design Language (XDL) to the Precharge Absorbed DPL (PA-DPL) format. Users can fully or partially convert the circuit in arbitrary placement schemes, without concerning the routing conflicts. Another significance is that this proposal is potentially to be used to other circuits that require precise routing control. SCA Security verification to an 8-bit AES coprocessor on SASEBO-GII indicates enhanced security grade due to the rigorous routing networks achieved by the repair process. Timing analysis further demonstrates that the net delay differences between complementary nets are minimized.
机译：双轨预充电逻辑（DPL）已被广泛研究为缓解侧通道攻击（SCA）威胁的有效对策类别，其中对运行中的加密设备的有害物理泄漏进行了检查和分析，以检索机密数据。 DPL协议要求在相应的导轨之间进行补偿，这与常规的逻辑原理不同。因此，它需要不寻常的设计流程以及重复繁琐的工作量。在本文中，我们提供了一个自定义执行工具来自动实现双轨逻辑。这种可控的自动化设计流程依靠Xilinx FPGA平台来获得具有高度对称网络的双轨。该工具能够自动将逻辑从Xilinx设计语言（XDL）上的原始单轨转换为预充电吸收DPL（PA-DPL）格式。用户可以以任意放置方案完全或部分转换电路，而无需考虑布线冲突。另一个意义是该建议可能会用于需要精确路由控制的其他电路。在SASEBO-GII上对8位AES协处理器进行的SCA安全性验证表明，由于修复过程实现了严格的路由网络，因此提高了安全等级。时序分析进一步表明，互补网络之间的网络延迟差异最小。

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