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首页> 外文期刊>Information Security, IET >Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis
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Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

机译：路由修复的基于平衡单元的平衡双轨逻辑针对边信道分析的复杂安全性验证

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摘要

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.
机译：常规的双轨预充电逻辑遭受难以获得双轨结构的严格实现的双重轨结构的影响。作为轻量级和高速双轨样式，基于平衡单元的双轨逻辑（BCDL）使用具有全局预充电信号的同步复合门来提供对差分功率或电磁分析的高抵抗力。 BCDL可以从具有约束条件的通用现场可编程门阵列（FPGA）设计流程中实现。然而，由于路由控制的灵活性不足，路由仍然存在，这不利地导致了安全敏感部件中互补网络之间的偏差。在本文中，基于路由修复技术，提出了对路由效果的新颖验证。在Xilinx Virtex-5 FPGA中基于块随机存取存储器（RAM）的BCDL上构建了一个8位简化的高级加密处理（AES）协处理器。由于不平衡的路由是BCDL的主要缺陷，因此作者可以排除其他影响并公平地量化安全性变体。针对具有连续路由方案的一组电路启动了一系列渐近相关电磁（EM）分析，以能够验证路由对边信道分析的影响。在修复了不相同的路由之后，将执行相互信息分析以进一步验证从BCDL中的相同路由对获得的具体安全性提高。

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