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Efficient separable convolution using field programmable gate arrays

机译：使用现场可编程门阵列进行有效的可分离卷积

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摘要

Two-dimensional (2D) convolution is an essential component in several image and video processing applications. The convolution operation is computationally expensive due to the large number of required additions and multiplications. Field Programmable Gate Array (FPGA) architectures have been used to mitigate this problem owing to their parallel processing capabilities. Using separable filter kernels can further improve the convolution operation both in terms of resource utilization and speed. Although several 2D convolution implementations have been presented in the literature, research on separable convolution using FPGA is limited.This paper presents a new separable FPGA-based convolution architecture. The goal is to reduce both on-chip resource utilization and external memory bandwidth for a given processing rate of the convolution unit. External memory bandwidth (EMB) and on-chip resource utilization are reduced by reusing common data shared by consecutive processing windows in a novel way. Comparisons with existing separable convolution methods demonstrate improvements offered by the proposed technique in terms of on-chip resource utilization and power consumption. (C) 2019 Elsevier B.V. All rights reserved.
机译：二维（2D）卷积是几种图像和视频处理应用程序中的重要组成部分。由于大量所需的加法和乘法，卷积运算在计算上是昂贵的。由于它们的并行处理能力，现场可编程门阵列（FPGA）体系结构已被用来缓解此问题。使用可分离的过滤器内核可以在资源利用率和速度方面进一步改善卷积操作。尽管文献中已经提出了几种2D卷积实现方法，但使用FPGA进行可分离卷积的研究仍然有限。本文提出了一种基于FPGA的新可分离卷积架构。目标是针对卷积单元的给定处理速率降低片上资源利用率和外部存储器带宽。通过以新颖的方式重用连续处理窗口共享的公共数据，可以减少外部存储器带宽（EMB）和片上资源的利用率。与现有可分离卷积方法的比较表明，在片上资源利用和功耗方面，所提出的技术提供了改进。 （C）2019 Elsevier B.V.保留所有权利。

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