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TileNET: Hardware accelerator for ternary Convolutional Neural Networks

机译：Tilenet：三元卷积神经网络的硬件加速器

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摘要

Convolutional Neural Networks (CNNs) are popular in Advanced Driver Assistance Systems (ADAS) for camera perception. The versatility of the algorithm makes it applicable in multiple applications like object detection, lane detection and semantic segmentation. For image processing to be viable in driver assistance systems, the throughput requirement ranges in the order of a few tens of TeraMACs per second (TMACs). In addition, high accuracy levels of image detection and recognition cannot be compromised for the need for high throughput. In this paper, we present TileNET, a novel tiled architecture for ternary-weighted CNNs. TileNET is modular and scalable across variations in network organization and device configurations. Two modes of the implementation are presented, viz., systolic and streaming. A high-level estimation technique has been developed that facilitates fast performance evaluation through design space exploration among a range of target devices and varying CNN models. Performance has been verified for area and throughput estimation for Xilinx Virtex, Artix, Kintex and Zynq devices. TileNET implemented on Virtex-7 (XC7VX1140T) results in a throughput of about 16 Teraoperations per second (TOPs) for LeNet, AlexNet, ResNet-50 and VGG-16. In addition, the 45nm standard cell implementation of TileNet shows a throughput of about 30 TOPs respectively.
机译：卷积神经网络（CNNS）在高级驾驶员辅助系统（ADAS）中受到相机感知的流行。算法的多功能性使其适用于物体检测，车道检测和语义分割等多种应用中。对于在驾驶员辅助系统中可行的图像处理，吞吐量要求按每秒几十三米（TMAC）的量级。此外，对于高吞吐量，不能妥协图像检测和识别的高精度水平。在本文中，我们呈现Tilenet，一种用于三元加权CNN的新型瓷砖架构。 TileNet在网络组织和设备配置中的变化中是模块化的并且可扩展。呈现了两种实施方式，viz，收缩和流。已经开发了一种高级估计技术，这是通过在一系列目标设备之间的设计空间探索和改变CNN模型之间的设计空间探索进行快速性能评估。 Xilinx Virtex，Artix，Kintex和Zynq设备的区域和吞吐量估计已验证了性能。在Virtex-7（XC7VX1140T）上实现的Tilenet导致每秒约16个TeraOperations（上部）的吞吐量，用于Lenet，AlexNet，Resnet-50和VGG-16。此外，Tilenet的45nm标准电池实施分别显示了约30个上的吞吐量。

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