Low-Loss Air-Cavity Through-Silicon Vias (TSVs) for High Speed Three-Dimensional Integrated Circuits (3-D ICs)

Liu Xiaoxian; Zhu Zhangming; Yang Yintang; Ding Ruixue

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Low-Loss Air-Cavity Through-Silicon Vias (TSVs) for High Speed Three-Dimensional Integrated Circuits (3-D ICs)

机译：适用于高速三维集成电路（3-D IC）的低损耗气腔硅通孔（TSV）

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Since the coupling loss of conventional low resistivity silicon (LRSi) is considerable in high speed three-dimensional integrated circuits (3-D ICs), air-cavity through-silicon vias (TSVs) on LRSi are proposed in this letter to reduce the conductive substrate losses for microwave applications. The -factor and insertion loss are exploited to assess the effect of air-cavity TSVs. The accurate wideband equivalent circuit model and simplified -model are derived based on the physical design parameters, which are established by the ADS software. Well agreements between the proposed models and 3-D full-wave EM field simulation of Ansoft's HFSS are shown with the operating frequencies up to 20 GHz.

机译：由于传统的低电阻硅（LRSi）在高速三维集成电路（3-D IC）中的耦合损耗相当大，因此在这封信中提出了LRSi上的气孔硅通孔（TSV）以减少导电性微波应用中的基板损耗。利用-因子和插入损耗来评估气孔TSV的效果。根据物理设计参数得出精确的宽带等效电路模型和简化模型，这些参数是由ADS软件建立的。所显示的模型与Ansoft HFSS的3-D全波EM场仿真之间的良好一致性在工作频率高达20 GHz时显示出来。

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《Microwave and Wireless Components Letters, IEEE》 |2016年第2期|89-91|共3页
作者
Liu Xiaoxian; Zhu Zhangming; Yang Yintang; Ding Ruixue;
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正文语种 eng
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Equivalent-circuit model; high speed three-dimensional integrated circuits (3-D ICs); low loss air-cavity through-silicon vias (TSVs);

机译：等效电路模型;高速三维集成电路（3-D IC）;低损耗的空孔硅通孔（TSV）;

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专利

1. Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits [J] . Ioannis Savidis, Syed M. Alam, Ankur Jain, Microelectronics journal . 2010,第1期

机译：3-D集成电路的硅通孔（TSV）的电气建模和表征
2. Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures [J] . Y. Yang, R. Labie, F. Ling, Microelectronics & Reliability . 2010,第9a11期

机译：用于三维堆叠集成电路（3D-SIC）架构的铜硅通孔（TSV）的工艺评估和附着力评估
3. Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits [J] . Xiaoxian Liu, Zhangming Zhu, Yintang Yang, 中国物理：英文版 . 2016,第011期

机译：高速三维集成电路中气隙贯穿硅通孔的寄生效应
4. Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits [C] . Weerasekera Roshan, Grange Matt, Pamunuwa Dinesh, . 2009

机译：三维（3-D）集成电路中硅通孔（TSV）的紧凑建模
5. Through-Silicon Via (TSV) Related Noise Coupling in Three-Dimensional (3-D) Integrated Circuits (ICs). [D] . Asgari, Mohammad Hosein. 2011

机译：三维（3-D）集成电路（IC）中的硅通孔（TSV）相关噪声耦合。
6. Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV) [O] . Wen-Wei Shen, Kuan-Neng Chen 2017

机译：三维集成电路（3D IC）关键技术：硅通孔（TSV）
7. Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs). [O] . Weerasekera Roshan, Pamunuwa Dinesh B., Grange M., 2009

机译：3-D集成电路（IC）中硅直通（TSV）寄生的闭合形式方程式。

Low-Loss Air-Cavity Through-Silicon Vias (TSVs) for High Speed Three-Dimensional Integrated Circuits (3-D ICs)

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