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首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation
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Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation

机译：性能和能源感知异构3D片上网络架构生成

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摘要

Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore, the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the existing solutions.
机译：最近，通过硅片通过（TSV）在3D片上网络（3D NoC）中​​提供更快的层间通信已变得更加流行。然而，TSV的面积开销降低了晶片利用率和良率，这影响了使用大量TSV（例如同质3D NoC拓扑）的3D架构的设计。而且，3D路由器需要更多的内存，因此比传统的2D路由器更耗电。或者，混合3D NoC通过使用有限数量的TSV结合了2D和3D路由器体系结构的面积和性能优势。现有的混合体系结构由于没有考虑不同应用程序的动态通信模式及其NoC资源使用情况而遭受更高的数据包延迟。我们提出了一种新颖的算法，可以针对给定的应用系统地生成混合3D NoC拓扑，以便在不牺牲NoC性能的情况下将垂直连接最小化。所提出的算法通过有效地重新分配垂直链接和缓冲区空间来分析目标应用程序并生成混合体系结构。此外，已经使用合成和各种实际流量模式对算法进行了评估。实验结果表明，与现有解决方案相比，该算法生成的优化架构具有较低的能耗，并显着减少了分组延迟。

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