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首页> 外文期刊>Proceedings of the institution of mechanical engineers >A low-power digital processing circuit for capacitive accelerometer
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A low-power digital processing circuit for capacitive accelerometer

机译：电容式加速度计的低功耗数字处理电路

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摘要

A low power consumption digital processing circuit with large dynamic range and low noise density for micromachined capacitive accelerometer is proposed. To reduce the power consumption, the sampling rate and the number of logic units used are analyzed. We lower the sampling rate to 2.5 MHz that is only 1/16 of previous scheme. At this frequency, the dynamic range is still as high as 120 dB that has been tested, while the dynamic power is as low as 5.4 mW that is only about 1/16 of previous scheme. To reduce the amount of logic units, we adopt square-wave demodulator instead of sinusoidal demodulator (realized by coordinate rotation digital computer algorithm). The entire digital processing circuit with square-wave demodulator uses 577 slice registers, about 1/10 of the circuit with sinusoidal demodulator. The dynamic power is even reduced to 0.54 mW. Most of all, almost no additional noise is added into this circuit, and the output noise density is as low as 0.01 mg/(Hz)~(1/2).
机译：提出了一种用于微加工电容式加速度计的动态范围大，噪声密度低的低功耗数字处理电路。为了降低功耗，分析了采样率和所用逻辑单元的数量。我们将采样率降低到2.5 MHz，仅为先前方案的1/16。在此频率下，动态范围仍然经过测试，高达120 dB，而动态功率则低至5.4 mW，仅为先前方案的1/16。为了减少逻辑单元的数量，我们采用方波解调器代替正弦解调器（通过坐标旋转数字计算机算法实现）。整个带方波解调器的数字处理电路使用577个切片寄存器，大约是正弦波解调器电路的1/10。动态功率甚至降低到0.54 mW。最重要的是，几乎没有额外的噪声添加到该电路中，并且输出噪声密度低至0.01 mg /（Hz）〜（1/2）。

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