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Low power BIST

机译：低功耗BIST

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摘要

In the last years designers have mainly concentrated on low power consumption in mobile computing devices and cellular phones. In this paper, new solutions for reducing the switching activity of BIST environment for the scan-organized Built-in Self-Test (BIST) architectures is presented. The key idea behind this technique is based on the design of a new structure of LFSR to generate more than one pseudo random bit per one clock pulse. Theoretical calculations were hardware verified in two digital system design environments: WebPACK ISE by Xilinx and Quartus Ⅱ by Altera. Power consumption measure tools were Xilinx XPower and Altera PowerPlay Power Analyzer Tool. The practical verification covers the power consumption of the Test Pattern Generator (TPG) as well as the complete BIST. The obtained results are over a dozen percent better compared to similar works.
机译：在过去的几年中，设计人员主要集中在移动计算设备和蜂窝电话的低功耗上。本文针对扫描组织的内置自测（BIST）架构，提出了减少BIST环境切换活动的新解决方案。这项技术背后的关键思想是基于一种新的LFSR结构的设计，该结构每一个时钟脉冲产生一个以上的伪随机位。理论计算在两个数字系统设计环境中进行了硬件验证：Xilinx的WebPACK ISE和Altera的QuartusⅡ。功耗测量工具是Xilinx XPower和Altera PowerPlay功耗分析器工具。实际验证涵盖了测试码型发生器（TPG）以及整个BIST的功耗。与类似的作品相比，获得的结果要好百分之十几。

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