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Enhanced Digital Synthesized Phase Locked Loop with High Frequency Compensation and Clock Generation

机译：具有高频补偿和时钟生成的增强数字合成锁相环

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摘要

The proposed work concentrates on the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm ×0.8 mm is implemented in a 0.18 μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are − 113.76 and − 105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is − 187.2 dBc/Hz (decibels relative to carrier). Closed form equations allow for a performance driven design for both PLL and estimator. By using a variable sample frequency controlled by the PLL, the Kalman filter is always operated around its center frequency, which is the rated grid frequency. The new topology is compared to other published single-phase PLL designs and its operation is verified by both simulations and experiments. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops. The PLL designed using dual mode logic technique exhibits excellent performance even under severely distorted utility grid voltage conditions. This robustness makes it very suitable for use in systems connected to grids having an important share of non-linear loads.
机译：所提出的工作集中在8-GHz电压控制振荡器（VCO）和24 GHz本地振荡器产生的频率三倍的集成。通过用电流重用拓扑堆叠VCO和三倍，可以保存该集成的功耗。具有0.7mm×0.8mm的总芯片面积的所提出的电路在0.18μmCMOS过程中实现。随着调谐电压从0到2 V增加，VCO的测量频率调谐范围（FTR）为7.06至8.33GHz。最终产生的输出频率从三倍数到21.18到24.98GHz（16.5％FTR）。核心电路完全消耗5 mA，从1.8V电源电压。当VTune为0 V时，VCO和频率三倍输出处的测量相位噪声分别为1-MHz偏移频率为113.76和-105.1 DBC / Hz。使用调谐的最佳评估值为-187.2 DBC / Hz（相对于载体分贝）。封闭形式方程允许PLL和估算器的性能驱动设计。通过使用由PLL控制的可变样本频率，Kalman滤波器始终围绕其中心频率运行，即额定电网频率。将新拓扑与其他公开的单相PLL设计进行比较，其操作都通过模拟和实验验证。 VCO和频率三倍体的这种集成具有高功率24-GHz锁相环中使用的高潜力。使用双模逻辑技术设计的PLL即使在严重扭曲的公用电网电压条件下也表现出优异的性能。这种稳健性使其非常适合在连接到具有非线性载荷的重要份额的网格的系统中使用。

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