A 3.3-V 800-nV/sub rms/ noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique

Nicollini G.; Guardiani C.

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A 3.3-V 800-nV/sub rms/ noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique

机译：采用成品率建模技术的3.3V 800nV / sub rms /噪声，增益可编程CMOS麦克风前置放大器设计

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A 3.3-V CMOS low-noise gain-programmable microphone amplifier with a high-impedance balanced input is presented. The preamplifier allows gains from 20 to 35 dB to be set by software control in 1-dB steps with 0.05-dB accuracy. Typical measured V/sub OS/ is 0.8 mV, V/sub OS/ drift is 1 mu V/C, input-referred p-weighted noise is 0.8 mu V/sub rms/ and total harmonic distortion (THD) is -70 dB. The active area is about 350 mils/sup 2/, and power consumption is 1.7 mW at 3.3-V supply and 2.9 mW at 5-V supply. These results have been obtained through an intensive use of the yield modeling technique for yield-performance optimization during the design phase, and by applying a common-centroid cross-coupled strategy to the layout of all the ideally matched MOS transistors in the input stage.

机译：提出了具有高阻抗平衡输入的3.3V CMOS低噪声增益可编程麦克风放大器。前置放大器允许通过软件控制以1 dB的步长以0.05 dB的精度设置20至35 dB的增益。典型测量的V / sub OS /为0.8 mV，V / sub OS /漂移为1μV/ C，输入参考p加权噪声为0.8μV / sub rms /，总谐波失真（THD）为-70 dB 。有效区域约为350 mils / sup 2 /，在3.3V电源时的功耗为1.7mW，在5V电源时的功耗为2.9mW。通过在设计阶段大量使用良率建模技术来优化良率性能，以及在输入阶段对所有理想匹配的MOS晶体管的布局应用共质心交叉耦合策略，即可获得这些结果。

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《IEEE Journal of Solid-State Circuits》 |1993年第8期|P.915-921|共7页
作者
Nicollini G.; Guardiani C.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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A 3.3-V 800-nV/sub rms/ noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique

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