A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Kim Dongwook; Ahmed Mostafa G.; Choi Woo-Seok; Elkholy Ahmed; Hanumolu Pavan Kumar

首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

【24h】

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

机译：12-GB / S 10-NS接通时间快速开/关波特率DFE接收器，在65纳米CMOS中

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a baud-rate ROO receiver that can turn on in just 10 ns (similar to 120 UI). Baud-rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER < 10(-12) and achieves a >30-MHz JTOL corner, 377 f s(rms) recovered clock jitter, and 3.8-pJ/bit energy efficiency.

机译：快速开/关（ROO）操作可根据链接利用率帮助缩放功率。在本文中，我们提出了一个可以在仅10 ns（类似于120 UI）的Baud率Roo接收器。使用新的定时函数来实现波特率时钟和数据恢复（CDR），该功能可用于使用环路未滚动判定反馈均衡器（DFE）的操作。通过在每个上电事件下偏移数字控制的振荡器（DCO）频率，通过在接收的数据位扫描恢复的时钟相位来快速打开接收器。该第一ROO DFE接收器还包括连续时间线性均衡器（CTLE）和三次点击DFE，以补偿奈奎斯特的高达20-DB通道损耗。原型接收器在65纳米CMOS工艺中制造，使用BER <10（-12）恢复12 GB / s，并达到> 30-MHz JTOL角，377 FS（RMS）恢复的时钟抖动，以及3.8-PJ /位能源效率。

著录项

来源
《IEEE Journal of Solid-State Circuits》 |2020年第8期|2196-2205|共10页
作者
Kim Dongwook; Ahmed Mostafa G.; Choi Woo-Seok; Elkholy Ahmed; Hanumolu Pavan Kumar;
展开▼
作者单位

Apple Inc West Lake Hills TX 78746 USA;

Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA;

Seoul Natl Univ Dept Elect & Comp Engn Seoul 08826 South Korea;

Broadcom Corp Irvine CA 92618 USA;

Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Timing; Receivers; Clocks; Decision feedback equalizers; Gain; Insertion loss; Baud rate; burst mode; clock and data recovery (CDR); decision feedback equalizer (DFE); rapid ON; OFF (ROO);

机译：时间;接收器;钟表;判定反馈均衡器;收益;插入损失;波特率;爆发模式;时钟和数据恢复（CDR）;判决反馈均衡器（DFE）;迅速（roo）;

相似文献

外文文献
中文文献
专利

1. A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS [J] . Kiran Shiva, Cai Shengchang, Luo Ying, IEEE Journal of Solid-State Circuits . 2019,第3期

机译：基于52 Gb / s ADC的PAM-4接收器，具有比较器辅助的2位/级SAR ADC和部分展开的65nm CMOS DFE
2. A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS [J] . Roshan-Zamir Ashkan, Iwai Takayuki, Fan Yang-Hang, IEEE Journal of Solid-State Circuits . 2019,第3期

机译：具有低开销技术的56 Gb / s PAM4接收器，用于在65 nm CMOS中对阈值和基于边缘的DFE FIR和IIR-Tap进行自适应
3. A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS [J] . Oh T., Harjani R. IEEE Journal of Solid-State Circuits . 2013,第6期

机译：在65 nm CMOS中使用MIMO串扰消除和信号重用的12 Gb / s多通道I / O
4. A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology [C] . Dickson Timothy O., Liu Yong, Rylov Sergey V., IEEE Custom Integrated Circuits Conference . 2014

机译：具有32nm SOI CMOS技术的DFE接收器的1.4pJ / b，可扩展功率的16×12-Gb / s源同步I / O
5. 4Gbps CMOS backplane receiver with adaptive blind DFE. [D] . Milijevic, Slobodan. 2007

机译：具有自适应盲DFE的4Gbps CMOS背板接收器。
6. A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS [O] . Siamak Sarvari, Tina Tahmoureszadeh, Ali Sheikholeslami, 2013

机译：5Gb / s投机性DFE，用于2个基于65nm CMOS的基于ADC的盲接收器

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

摘要

著录项

相似文献

相关主题

期刊订阅