A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology

Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Peter Buchmann; Marcel Kossel; Thomas Morf; Jonas Weiss; Martin L. Schmatz

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A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology

机译：采用90 nm CMOS SOI技术的22 Gb / s PAM-4接收器

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摘要

We report a receiver for four-level pulse-amplitude modulated (PAM-4) encoded data signals, which was measured to receive data at 22 Gb/s with a bit error rate (BER) < 10{sup}(-12) at a maximum frequency deviation of 350 ppm and a 2{sup}7 - 1 PRBS pattern. We propose a bit-sliced architecture for the data path, and a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. We present a novel method to characterize sampling latches and include them in the data path. A current-mode logic (CML) biasing scheme using programmable matched resistors limits the effect of process variations. The receiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. The measured current consumption is 207 mA from a 1.1-V supply, and the active chip area is 0.12 mm{sup}2.

机译：我们报告了一种用于四电平脉冲幅度调制（PAM-4）编码数据信号的接收器，该接收器经测量以22 Gb / s的速率接收数据，误码率（BER）<10 {sup}（-12）在最大频率偏差为350 ppm，并具有2 {sup} 7-1的PRBS模式。我们提出了一种用于数据路径的位分片架构，以及一种新型的电压移位放大器，以向差分数据信号引入可编程偏移。我们提出了一种新颖的方法来表征采样锁存器并将它们包括在数据路径中。使用可编程匹配电阻器的电流模式逻辑（CML）偏置方案限制了工艺变化的影响。接收器还具有可编程信号终端，模拟均衡器和每个采样锁存器的失调补偿。从1.1V电源测得的电流消耗为207 mA，有源芯片面积为0.12 mm {sup} 2。

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来源
《IEEE Journal of Solid-State Circuits》 |2006年第4期|p.954-965|共12页
作者
Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Peter Buchmann; Marcel Kossel; Thomas Morf; Jonas Weiss; Martin L. Schmatz;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CML; CMOS; Digital communication; Latch; PAM-4; Receiver; Serial links; SOI;

机译：CML;CMOS;数字通信;锁存器;PAM-4;接收器;串行链路;SOI;

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1. A Flip-Chip-Assembled W-Band Receiver in 90-nm CMOS and IPD Technologies [J] . Li Chun-Hsing, Hsieh Wan-Ting, Chiu Te-Yen IEEE Transactions on Microwave Theory and Techniques . 2019,第4期

机译：采用90nm CMOS和IPD技术的倒装芯片组装W波段接收器
2. A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability [J] . Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, IEEE Transactions on Electron Devices . 2007,第期

机译：浮体单元，完全兼容用于128 Mb SOI DRAM的90 nm CMOS技术节点，并且具有可扩展性
3. A 243-GHz F{sub}t and 208-GHz F{sub}(max), 90-nm SOI CMOS SoC Technology With Low-Power mm Wave Digital and RF Circuit Capability [J] . Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, IEEE Transactions on Electron Devices . 2005,第7期

机译：具有低功耗毫米波数字和RF电路功能的243 GHz F {sub} t和208 GHz F {sub}（max），90 nm SOI CMOS SoC技术
4. A 22 Gbit/s PAM-4 receiver in 90 nm CMOS-SOI technology [C] . Toifl, T., Menolfi, VLSI Circuits, 2005 IEEE Symposium on . 2005

机译：采用90 nm CMOS-SOI技术的22 Gbit / s PAM-4接收器
5. A differential-based multiple bit rate PSK receiver: Theory, architecture, and SOI CMOS implementation. [D] . Yuce, Mehmet Rasit. 2004

机译：基于差分的多比特率PSK接收器：理论，体系结构和SOI CMOS实现。
6. Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology [O] . Maria Malits, Yael Nemirovsky 2017

机译：CMOS-SOI技术中的纳米集成温度和热传感器
7. A Highly-Integrated Reconfigurable Ka-Band Receiver Supporting Active and Passive Detections in a 90-nm CMOS Technology [O] . Chun-Hsing Li, Ke-Deng Huang, Te-Yen Chiu 2021

机译：一种高度集成的可重构KA波段接收器，支持90nm CMOS技术中的主动和被动检测

A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology

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