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A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC

机译:CMOS 1 / spl times / -16 / spl times / speed DVD写通道IC

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摘要

Optical recording demands a meticulous write strategy to control the laser beam power and regulate the phase change layer temperature tightly. The width, height, and delay of a string of short pulses applied to the laser diode need to be adjusted in fine steps, and the writing speed varies widely per applications. A multi-phase phase-locked loop (PLL) tracks a wide range of clock frequencies, and provides a low-jitter time base for write pulses. With two enabling circuit concepts, PLL loop filter voltage folding/unfolding and switch-in of parallel MOS resistors in delay cells, it is possible to operate a PLL to cover a frequency range spanning over three octaves with one VCO. A 10-stage differential VCO is phase-locked to the input channel clock ranging from 26 to 420 MHz (1/spl times/-16/spl times/ DVD speed), and its 20-phase outputs are used to generate write pulses. The pulsewidth and delay are programmed with 120 /spl plusmn/ 40 ps time resolution. The prototype chip fabricated in 0.35 /spl mu/m CMOS occupies 3.5/spl times/3.3 mm/sup 2/, and consumes 294 mW at 3.3 V.
机译:光学记录需要精心的写入策略,以控制激光束功率并严格调节相变层温度。施加在激光二极管上的一串短脉冲的宽度,高度和延迟需要进行精细调整,并且写入速度会因应用而有很大差异。多相锁相环(PLL)跟踪各种时钟频率,并为写脉冲提供了低抖动的时基。利用两个使能电路概念,PLL环路滤波器的电压折叠/展开以及延迟单元中并联MOS电阻的接通,可以使用一个VCO操作PLL来覆盖跨越三个八度音阶的频率范围。一个10级差分VCO锁相到输入通道时钟,范围为26至420 MHz(1 / spl次/ -16 / spl次/ DVD速度),其20相输出用于生成写脉冲。脉冲宽度和延迟的编程时间分辨率为120 / spl plusmn / 40 ps。以0.35 / spl mu / m CMOS制造的原型芯片占3.5 / spl次/3.3 mm / sup 2 /,在3.3 V时消耗294 mW。

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