...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Solid-State Electronics >Capacitance analysis of devices with electrically floating regions
【24h】

Capacitance analysis of devices with electrically floating regions

机译：具有电浮区的器件的电容分析

获取原文
获取原文并翻译 | 示例
   

获取外文期刊封面封底 >>

       
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Operation mechanisms of devices with electrically floating regions have been analyzed by device simulations. An insulator has been modeled as a wide-gap semiconductor and the device simulation has been carried out in the whole region including insulator and floating regions. By using this approach, we have evaluated electrical properties of the capacitances used to represent such devices; i.e., the capacitance of interconnect structures with metal-fill and the drain capacitance of an advanced SOI-MOSFET with an electrically floating interlayer. When one-fourth of an insulating area between parallel interconnect-lines is occupied by a squared fill, the capacitance between the lines was found to increase by three-fourths, over the value for a parallel plate capacitance without dummy fills. Also, the drain capacitance of an advanced SOI-MOSFET structure, i.e., a Si/oxide/poly-Si/oxide/ Si-substrate, was analyzed. When the doping concentration of the electrically floating poly-Si interlayer is not so high, the interlayer is partially depleted and a depletion capacitor is formed. The floating potential varies non-linearly with the applied bias and is smaller than the bias. The total capacitance of a multi-oxide-layered SOI-MOSFET structure is much lower than the MOS capacitance estimated from the oxide thickness. Floating elements have great advantages in terms of decreasing capacitance values.
机译：通过器件仿真分析了具有电浮区的器件的工作机理。已将绝缘体建模为宽隙半导体，并在包括绝缘体和浮置区的整个区域中进行了器件仿真。通过使用这种方法，我们评估了用于表示此类设备的电容的电性能；即具有金属填充物的互连结构的电容和具有电浮动中间层的先进SOI-MOSFET的漏极电容。当平行互连线之间的绝缘面积的四分之一被正方形填充物占据时，发现线之间的电容增加了四分之三，超过了没有虚设填充的平行板电容的值。而且，分析了先进的SOI-MOSFET结构，即Si /氧化物/多晶硅/氧化物/ Si衬底的漏极电容。当电浮动多晶硅中间层的掺杂浓度不是很高时，该中间层部分耗尽并且形成耗尽电容器。浮动电位随施加的偏压非线性变化，并且小于偏压。多氧化物层SOI-MOSFET结构的总电容远低于根据氧化物厚度估算的MOS电容。浮动元件在减小电容值方面具有很大的优势。

著录项

  • 来源
    《Solid-State Electronics》 |2004年第12期|p.2115-2124|共10页
  • 作者

    Ken Yamaguchi; Masatada Horiuchi;

  • 作者单位

    Central Research Laboratory, Hitachi Ltd., Tokyo 185-8601, Japan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 一般性问题;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号