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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection
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An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

机译：通过流水线故障检测减少测试时间和测试功率的重叠扫描架构

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摘要

We present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works where the scan chain is partitioned only based on the excitation properties of the flip-flops (FFs), our work considers both the excitation and propagation properties of the scan FFs. In the proposed scan architecture, the scan chain is partitioned to maximize the overlapping between the excitation and propagation on different fault sets. The scan architecture also allows the entire set of detectable faults in the circuit under test (CUT) to be detected with only a portion of the scan elements active at a time, and thereby completely eliminates the need for the "serial full-scan" mode which is inefficient for both the test time and test power. Experimental results show that by introducing minimal hardware overhead, and without sacrificing fault coverage, an average peak power reduction of 22.8%, average power reduction of 41.6%, and an average reduction of 18.5% on the test application time can be achieved, compared with the ordinary full-scan architecture
机译：我们提出了一种新颖的扫描架构，可同时减少测试应用程序的时间和测试功率（均值和峰值功率）。与以前的工作仅基于触发器（FF）的激励特性对扫描链进行分区的工作不同，我们的工作同时考虑了扫描FF的激励和传播特性。在所提出的扫描架构中，扫描链被分割以最大化激发和传播在不同故障集上的重叠。扫描架构还允许在一次仅激活一部分扫描元件的情况下，检测被测电路（CUT）中的整个可检测故障集，从而完全消除了对“串行全扫描”模式的需求这对于测试时间和测试功率均无效。实验结果表明，与引入的硬件相比，通过引入最小的硬件开销，并且不牺牲故障覆盖率，平均峰值功耗降低了22.8％，平均功耗降低了41.6％，平均降低了18.5％的测试应用时间。普通的全扫描架构

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