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首页> 外文期刊>Journal of Low Power Electronics >A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction
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A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction

机译：用于测试电源和测试时间的新型电源管理扫描架构

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摘要

In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. This paper proposes a Power-Managed Scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. Some practical implementation challenges that arise when the proposed scheme is employed on industrial designs are also discussed. Experimental results on benchmark circuits and industrial designs show that employing the proposed technique leads to a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.
机译：在Sub-70 NM Technologies中，泄漏功率成为总功率的重要组成部分。 设计人员通过广泛使用自适应电压缩放技术来解决这种问题，以减少动态和漏电。 低功耗扫描测试方案在过去推出主要地址动态功率降低，并且在降低总功率方面不太有效。 本文提出了一种功率管理的扫描（PMSCAN）方案，它利用自适应电压缩放逻辑的存在以降低测试功率。 还讨论了在工业设计上采用拟议计划时出现的一些实际实施挑战。 基准电路和工业设计的实验结果表明，采用所提出的技术导致动态和漏电的显着降低。 所提出的方法还可以用作车辆，通过适当地调整扫描移位频率和扫描模式电源，通过测试功率来进行折衷测试施用时间。

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