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Parametric yield modeling using hidden variable logistic regression

机译：使用隐藏变量逻辑回归的参数收益建模

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Semiconductor manufacturing is composed of multistep manufacturing processes that includes wafer fabrication, wafer probing, circuit packaging, and final circuit testing. Through manufacturing, yield is defined as the proportion of semiconductor circuits on a wafer proved to function correctly and is used to represent productivity and quality. Yield is known to be affected by two major losses, the first loss being related to contaminants control and is called functional yield loss and the second is related to control for manufacturing steps, that are the series of operations employed to build structures on a circuit. The second loss is referred to as the parametric yield loss. Parametric yield loss occurs when a circuit fails to meet the exact structural specifications. Parametric yield, which has been less investigated than functional yield with respect to modeling methodologies and can be characterized by measuring dimensions of the structures themselves, dimensions between structures and dimensions of the materials used to form the structures. For instance the thickness of thin materials is considered as a primary critical dimension (CD) and is considered regularly. Such variables are called decision variables and the article considers continuous process variables only. A target in semiconductor industry is assumed to be a temporary value until reaching the manufacturing maturity. Initially in a corner point design, first experiments are conducted on combinations of diverse structural arrangements to get a good target value for a high yield. The knowledge of the factors affecting the yield is further improved by in-line measurements. However specifying the relationships may become difficult due to data collection problems. The yield data are collected for this study on the process variable and the wafer probe results. Locations on the wafer are predefined and the wafer probe results are binary data. One possible model is using logistic regression but has many limitations. Another issue is to determine the relationship between the observations and the response. Te third issue is that of missing data. This article proposes a correlation analysis method between a continuous predictor variable and a binary response variable by handling the data problems. (19 refs.)
机译：半导体制造由包括晶片制造，晶片探测，电路封装和最终电路测试的多步制造过程组成。在制造过程中，成品率定义为晶圆上半导体电路的比例，事实证明该晶圆能正确运行，并用来表示生产率和质量。已知产量受到两个主要损失的影响，第一个损失与污染物控制有关，称为功能性产量损失，第二个与制造步骤的控制有关，制造步骤是在电路上构建结构的一系列操作。第二种损失称为参数屈服损失。当电路无法满足确切的结构规格时，就会发生参数成品率损失。就建模方法而言，参数屈服比功能屈服受到的研究较少，并且可以通过测量结构本身的尺寸，结构之间的尺寸以及用于形成结构的材料的尺寸来表征。例如，薄材料的厚度被视为主要的临界尺寸（CD），并且被定期考虑。这些变量称为决策变量，本文仅考虑连续过程变量。假设半导体行业的目标是达到制造成熟之前的临时值。最初在角点设计中，首先对各种结构排列的组合进行了首次实验，以获得高产量的良好目标值。在线测量进一步提高了影响产量的因素的知识。但是，由于数据收集问题，指定关系可能会变得困难。对于该研究，收集了有关工艺变量和晶圆探针结果的成品率数据。晶片上的位置是预定义的，晶片探测结果是二进制数据。一种可能的模型是使用逻辑回归，但有很多局限性。另一个问题是确定观察结果与响应之间的关系。第三个问题是数据丢失。通过处理数据问题，本文提出了一种在连续预测变量和二进制响应变量之间的相关分析方法。 （19篇）

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