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Real Time Generation of the Quinquenary Pulse Compression Sequence using FPGA

机译：使用FPGA实时生成五次脉冲压缩序列

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摘要

Quinquenary codes have been widely used in radar and communication areas, but the design of Quinquenary codes with good merit factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. All these optimization algorithms have serious drawbacks of non guaranteed convergence, slow convergence rate and require large number of evaluations of the objective function. To overcome these drawbacks, recently we proposed an efficient VLSI architecture for identification of the Quinquenary Pulse compression sequences. Integrating this architecture with the currently proposing architecture provides an efficient real time Hardware solution for identification and generation of the Quinquenary Pulse compression sequences. This paper describes the real time generation of the Quinquenary Pulse compression sequences using Field Programmable Gate Array (FPGA). In this paper an effort is made for the generation of the Pulse compression sequences using an efficient VLSI architecture. The Proposed VLSI architecture is implemented on the FPGA as it provides the flexibility of reconfigurability and reprogrammability.
机译：五次码已广泛用于雷达和通信领域，但是具有优良品质因数的五次码设计是一个非线性的多变量优化问题，通常很难解决。为了解决上述问题，文献中报道了许多全局优化算法，例如遗传算法，模拟退火算法和隧穿算法。所有这些优化算法都有严重的缺点，即无法保证收敛，收敛速度慢，并且需要对目标函数进行大量评估。为了克服这些缺点，最近我们提出了一种有效的VLSI架构，用于识别五次脉冲压缩序列。将该体系结构与当前提出的体系结构集成在一起，可提供一种高效的实时硬件解决方案，用于识别和生成五次脉冲压缩序列。本文介绍了使用现场可编程门阵列（FPGA）实时生成五次脉冲压缩序列的过程。在本文中，人们致力于使用高效的VLSI架构来生成脉冲压缩序列。提议的VLSI架构在FPGA上实现，因为它提供了可重配置性和可重编程性的灵活性。

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