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Easy and difficult exact covering problems arising in VLSI power reduction by clock gating

机译：通过时钟门控在VLSI功耗降低中出现的容易和困难的精确覆盖问题

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摘要

Several graph matching and exact covering problems arising in VLSI low-power design optimization by clock gating are presented. To maximize the power savings, clock gating requires optimal grouping of Flip-Flops (FFs), which depends on FFs' data toggling correlations and probabilities. These naturally lead to optimal matching and exact covering problems. We present three problems arising by different clock-gating techniques. In a method called data-driven clock-gating, the corresponding covering problem is intractable but can practically be solved by appropriate heuristics. In another method called multi-bit flipflops, the covering problem is easily solvable in a closed-form, required only sorting. We finally present the covering problem arising in a new method called look-ahead clock-gating, for which the question of whether the exact covering problem is easy or difficult is left open.
机译：介绍了通过时钟门控在VLSI低功耗设计优化中出现的几种图形匹配和精确覆盖问题。为了最大程度地节省功耗，时钟门控需要对触发器（FF）进行最佳分组，这取决于FF的数据切换相关性和概率。这些自然会导致最佳匹配和确切的覆盖问题。我们提出了由不同的时钟门控技术引起的三个问题。在一种称为数据驱动时钟门控的方法中，相应的覆盖问题是棘手的，但实际上可以通过适当的启发式方法解决。在另一种称为多位触发器的方法中，覆盖问题很容易以封闭形式解决，只需分类即可。最后，我们介绍了一种称为“超前时钟门控”的新方法中出现的覆盖问题，对于该问题，确切的覆盖问题是容易还是很难解决。

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