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首页> 外文期刊>Journal of Low Power Electronics >A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits
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A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits

机译：一种数字电路布局级时钟选通优化的改进方法

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摘要

Power consumption of clock trees in modern VLSI designs is a dominant part of the total power budget. It is thus mandatory to keep it under control. This paper introduces an approach for reducing the clock power based on optimization of clock gating. In particular, in this work we focus on theory and application of the proposed methodology both on register (flip-flop) and latch based designs. Starting from a gate-level description of the design, the methodology automatically modifies the existing clock gating structure in order to generate a set of constraints for driving the construction of the clock tree by the clock synthesis tool. The methodology has been fully integrated into an industry-strength design flow. Experiments were performed on industrial designs for a real evaluation of the effectiveness of the technique and results show that a true improvement of power savings is achievable with respect to the standard clock gating.
机译：现代VLSI设计中时钟树的功耗是总功耗预算的主要部分。因此，必须对其进行控制。本文介绍了一种基于时钟门控优化的降低时钟功率的方法。特别地，在这项工作中，我们专注于在寄存器（触发器）和基于锁存器的设计上所提出的方法的理论和应用。从设计的门级描述开始，该方法自动修改现有的时钟门控结构，以生成一组约束，以通过时钟综合工具来驱动时钟树的构建。该方法已完全集成到具有行业实力的设计流程中。对工业设计进行了实验，以实际评估该技术的有效性，结果表明，相对于标准时钟门控，可以实现功耗的真正提高。

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