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首页> 外文期刊>Journal of Low Power Electronics >A 1.9 μW Transient-Enhanced Low-Dropout Regulator with Voltage-Spike Suppression
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A 1.9 μW Transient-Enhanced Low-Dropout Regulator with Voltage-Spike Suppression

机译：具有电压尖峰抑制功能的1.9μW瞬态增强型低压降稳压器

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摘要

A low-voltage low-dropout regulator (LDO) with voltage-spike suppression is presented in this paper. The proposed LDO is formed by multiple gain stages to improve the loop gain and loop bandwidth simultaneously. The LDO is compensated by a zero generated by the equivalent series resistance (ESR) of the output capacitor, as well as a zero created by the high-pass feedback network. Moreover, the structure contains a capacitive-coupling push-pull stage controlled by a voltage comparator to improve slew rate at the gate of the power transistor in order to suppress the output voltage spike without increasing the bias current. The proposed LDO is implemented by a 0.35-μm CMOS technology (V_(THN) ≈ 0.5 V and V_(THP) ≈ -0.65 V). The active area of the chip is 310 μm × 1010 μm. The minimum operating input voltage is 1 V and the preset output voltage is 0.9 V, with quiescent current of 1.9 μA. Measured maximum output current is 91 mA. Load transient measurement shows the voltage spike can be completely suppressed.
机译：本文提出了一种具有电压尖峰抑制功能的低压低压差稳压器（LDO）。所提出的LDO由多个增益级组成，以同时提高环路增益和环路带宽。 LDO由输出电容器的等效串联电阻（ESR）产生的零以及高通反馈网络产生的零来补偿。此外，该结构包含由电压比较器控制的电容耦合推挽级，以提高功率晶体管栅极的压摆率，从而在不增加偏置电流的情况下抑制输出电压尖峰。所提出的LDO是通过0.35-μmCMOS技术（V_（THN）≈0.5 V和V_（THP）≈-0.65 V）实现的。芯片的有效面积为310μm×1010μm。最低工作输入电压为1 V，预设输出电压为0.9 V，静态电流为1.9μA。测得的最大输出电流为91 mA。负载瞬态测量表明电压尖峰可以完全被抑制。

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