Reversible logic is an important alternate to reduce the power. Theoretically logical reversibility offers zero power consumption because the power taken from the source can be fed back to the source again. However its design demands some additional inputs (ancillary inputs) and garbage outputs. The main objective of this paper is to design a special class of multiplier using reversible circuits. This special class is applicable for the large operands and those are close to some base. We show that a method of ancient Indian mathematics is very effective in such kind of multiplication. We have proposed reversible designs of binary and BCD number system using signed arithmetic. We compare our design with that of a specific reversible multiplier that used ancient Indian mathematics and with another recent general reversible multiplier circuit. Our design offers better performance in respect of parametric estimation in comparison with earlier works.
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