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首页> 外文期刊>Journal of Low Power Electronics >Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic
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Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic

机译：基于低功耗FinFET的宽扇入Domino逻辑的新型NBTI感知方法

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摘要

As the VLSI technology is heading towards deep sub nanometer range NBTI effect has emerged as a major reliability issue for the CMOS as well as FinFET based circuits. NBTI causes an incremental deviation in the threshold voltage of PMOS and hence causes variation in timing of digital circuits. This timing mismatch is a serious issue for synchronous clock based circuits such as dynamic logic gates. Further NBTI may increase the delay of circuits which are lying in the critical path of a system and may lead to failure of system. This NBTI caused delay can be a serious issue for wide fan-in domino OR gate lying in the critical path of a microprocessor. In this paper the impact of NBTI on the FinFET based wide fan-in dynamic OR gate has been studied. A novel sensor based NBTI aware FinFET domino OR gate has also been proposed here. Proposed design makes use of FinFET back gate biasing technique to maintain a constant threshold voltage of the transistors. Proposed design is capable of maintaining a stable performance of domino OR gate with only 1.5% variation in delay for a lifetime of 10 years.
机译：随着VLSI技术走向深亚纳米范围，NBTI效应已成为CMOS以及基于FinFET的电路的主要可靠性问题。 NBTI会导致PMOS阈值电压的增量偏差，从而导致数字电路时序的变化。对于诸如动态逻辑门之类的基于同步时钟的电路，这种时序失配是一个严重的问题。此外，NBTI可能会增加位于系统关键路径中的电路的延迟，并可能导致系统故障。 NBTI引起的延迟对于位于微处理器关键路径中的宽扇形多米诺骨牌OR门可能是一个严重的问题。本文研究了NBTI对基于FinFET的宽扇入动态或门的影响。本文还提出了一种基于传感器的新型NBTI感知FinFET多米诺骨牌门。拟议的设计利用FinFET背栅偏置技术来保持晶体管的恒定阈值电压。提议的设计能够在10年的生命周期内仅以1.5％的延迟变化来维持Domino或Gate的稳定性能。

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