A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong

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A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

机译：采用0.18μmCMOS技术的超高速宽带折叠和内插模数转换器的数字校准技术

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摘要

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

机译：提出了一种采用0.18μmCMOS技术的超高速折叠内插模数转换器的数字校准技术。高3位闪存转换器和低5位折叠内插转换器采用了类似的数字校准技术，它们基于精心设计的校准基准，校准DAC和比较器。香料仿真和测量结果表明，对于高频宽带模拟输入，ADC禁用校准后产生5.9 ENOB，启用校准时产生7.2 ENOB。

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来源
《Journal of Semiconductors》 |2011年第1期|共8页
作者
Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong;
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正文语种 eng
中图分类无线电电子学、电信技术;
关键词
ultra high-speed; wide-bandwidth; folding; interpolating; analog-to-digital converter;

机译：超高速;宽带;折叠;插值;模数转换器;

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1. A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology [J] . Yu Jinshan, Zhang Ruitao, Zhang Zhengping, Journal of Semiconductors . 2011,第1期

机译：采用0.18μmCMOS技术的超高速宽带折叠和内插模数转换器的数字校准技术
2. Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter [J] . Kerz??rho V.Fresnaud V.Dallet D.Bernard S.Bossuet L. Instrumentation and Measurement, IEEE Transactions on . 2011,第3期

机译：用于模数转换器的整体非线性校正的快速数字后处理技术：在12位折叠和内插模数转换器上的验证
3. An 8-Bit 200MS/S CMOS Folding/Interpolating Analog-to-Digital Converter [J] . Seung-Chan HEO, Young-Chan JANG, Sang-Hune PARK, IEICE Transactions on Electronics . 2003,第4期

机译：一个8位200MS / S CMOS折叠/内插模数转换器
4. Digital calibration implementation for track-and-hold offset in a high-speed timing-interleaved folding and interpolating analog-to-digital converter [C] . 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology . 2010

机译：高速定时交错折叠和内插模数转换器中采样保持偏移的数字校准实现
5. Offset calibration techniques for high-speed CMOS flash analog-to-digital converters. [D] . Yao, Junjie. 2010

机译：高速CMOS闪存模数转换器的失调校准技术。
6. A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors [O] . Tao Lyu, Suying Yao, Kaiming Nie, 2014

机译：用于CMOS图像传感器的12位高速列并行两步单斜率模数转换器（ADC）
7. Design Techniques for Analog-to-Digital Converters in Scaled CMOS Technologies [O] . Kuppambatti Jayanth Narasimhan 2014

机译：比例CMOS技术中模数转换器的设计技术

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

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