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Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

机译：基于隧道FET的动态存储器克服较低感测距的缺点以及增强的电荷保持和可扩展性

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摘要

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 degrees C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of similar to 1.2 mu A mu m(-1) along with a longer retention time (RT) of similar to 1.8 s at 85 degrees C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.
机译：工作报告使用平面三栅极隧道场效应晶体管（TFET）以在85摄氏度下以增强的感测余量（SM）为动态存储器。与本质膜的部分区域的源极对齐的两种对称栅极（G1）导致更好的静电控制，该控制基于带 - 带隧道的读取机构，而另一个栅极（G2），位于第一前部相邻门负责电荷存储和寄托。所提出的架构导致与1.2μmm（-1）类似的增强型SM，以及在85摄氏度下类似于1.8秒的更长的保留时间（RT），总长度为600nm。朝向源的双栅架构增加了隧道电流，并且还降低了短信效应，增强了SM和可伸缩性，从而克服了基于TFET的动态存储器所面临的临界瓶颈。该工作还讨论了重叠/下划线和接口费用基于TFET的动态存储器的影响。设备操作的见解表明，适当的架构和偏差的选择不仅限制了SM和RT之间的折衷，而且还导致漏极电压和总长度分别缩小到0.8V和115nm之间的可扩展性。

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  • 来源
    《Nanotechnology》 |2017年第44期|共11页
  • 作者

    Navlakha Nupur; Kranti Abhinav;

  • 作者单位

    Indian Inst Technol Indore Discipline Elect Engn Low Power Nanoelect Res Grp Indore 453552 Madhya Pradesh India;

    Indian Inst Technol Indore Discipline Elect Engn Low Power Nanoelect Res Grp Indore 453552 Madhya Pradesh India;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 特种结构材料;
  • 关键词

    DRAM; retention time; sense margin;

    机译：DRAM;保留时间;感测余量;

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