Reusable Data-Path Architectures for EtM and MtE on FPGA

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Reusable Data-Path Architectures for EtM and MtE on FPGA

机译：FPGA上的ETM和MTE的可重用数据路径架构

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In this paper, reuse similar function blocks within different cryptography algorithms is proposed to reduce cryptography hardware footprints for resource-constraint devices such as Radio Frequency Identifier (RFID) and Internet of Things (IoT). Reusing similar components for differentprocesses such as encryption and authentication is possible since it is unnecessary to perform these two processes in a parallel manner. By adopting this approach, reusable data-path architectures is proposed for Encrypt-then-MAC (EtM) and MAC-then-Encrypt (MtE) that suit Field ProgrammableGate Array (FPGA) as an evaluation platform. The selected encryption algorithm is LED, while PHOTON is used to generate the MAC codes. The results show a throughput of 653 Mbps and efficiency of 0.76 Mbps/slices for EtM and MtE evaluated on a low-cost Spartan-3 FPGA.

机译：在本文中，提出了在不同加密算法中重用类似的功能块，以减少用于诸如射频标识符（RFID）和物联网（物联网）的资源约束设备的加密硬件占用。由于不需要以并行方式执行这两个过程，因此可以为诸如加密和认证等不同的处理来重用类似的组件。通过采用这种方法，提出了可重复使用的数据路径架构，用于加密-T'-MAC（ETM）和MAC-DOTER-CONRYPT（MTE），将现场编程阵列（FPGA）适用于评估平台。所选加密算法是LED，而Photon用于生成MAC代码。结果表明，在低成本的斯巴达-3 FPGA上评估了653 Mbps的吞吐量和0.76 Mbps /切片的效率。

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《Advanced Science Letters》 |2018年第1期|共5页
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正文语种 eng
中图分类工业技术;
关键词
Authenticated Encryption; Encrypt-then-MAC; FPGA; Lightweight Cryptography;

机译：经过身份验证的加密;加密-The-Mac;FPGA;轻量级密码学;

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专利

1. Reusable Data-Path Architectures for EtM and MtE on FPGA [J] . Advanced Science Letters . 2018,第1期

机译：FPGA上的ETM和MTE的可重用数据路径架构
2. FPGA based distributed self healing architecture for reusable systems [J] . Ali Akoglu, Adarsha Sreeramareddy, Jeff G. Josiah Cluster computing . 2009,第3期

机译：基于FPGA的可重用系统的分布式自我修复架构
3. FPGA based distributed self healing architecture for reusable systems [J] . Ali Akoglu, Adarsha Sreeramareddy, Jeff G. Josiah Cluster Computing . 2009,第3期

机译：基于FPGA的可重用系统的分布式自我修复架构
4. An FPGA architecture for data-path applications [C] . Furtek, F. . 1993

机译：用于数据路径应用的FPGA架构
5. Layer-type Specialized Processing Engines for a Semi-Streaming Convolutional Neural Network Hardware Architecture for FPGAs [D] . Shaydyuk, Nazariy. 2020

机译：用于FPGA的半流式卷积神经网络硬件架构的层型专业处理引擎
6. A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons [O] . Kaveh Akbarzadeh-Sherbaf, Behrooz Abdoli, Saeed Safari, 2018

机译：用于霍奇金-赫克斯利神经元随机连接网络的可扩展FPGA架构
7. A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization [O] . Parsons, Aaron, Backer, Donald, Chen, Henry, 2009

机译：基于模块化FpGa硬件的可扩展相关器架构，可重复使用的Gateware和数据打包
8. Proposed DoD Guidelines for Implementation of a Web-Based Joint IETM Architecture (JIA) to Assure the Interoperability of DoD IETMs [R] . Jorgensen, E. L. 1999

机译：提议实施基于Web的联合IETm架构（JIa）的国防部指南，以确保国防部IETm的互操作性

Reusable Data-Path Architectures for EtM and MtE on FPGA

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