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Design and analysis of high-speed split-segmented switched-capacitor DACs

机译：高速分割分段开关电容DAC的设计与分析

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摘要

In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area W-C (u) is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, C (u) ) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.
机译：为了实现开关电容（SC）数模转换器（DAC）的高速和高分辨率，提出了一种分割分段SC DAC的架构。数学地分析和建模KT / C噪声，电容失配，稳定时间和同时开关噪声的详细设计考虑因素。设计区域W-C（U）是基于该分析定义的。它不仅用于识别最大速度和分辨率，还用于找到SC DAC拓扑的某些速度和分辨率的设计点（W，C（U））。还考虑分割效果。这种类型的DAC的实施例是在65nm CMOS中设计的12位6-6个分割SC DAC。利用用于非线性取消的推导叠加技术的线性开环输出驱动器用于驱动SC阵列的片外负载而不会影响其性能。测量结果表明，SC DAC在输入信号的1 GHz带宽中实现了44 dB的杂散动态范围，同时消耗从1 V数字和1.2 V模拟物品的50 MW。由于制造芯片中的电源抑制比较低，测量从测量实现的整体性能比预期更差。该DAC可用于发射器基带进行宽带无线通信。

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