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首页> 外文期刊>Journal of Low Power Electronics >Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption
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Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption

机译：使用多电压元件进行低功耗的高电平设计电源优化技术

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摘要

Power reduction at the earliest stages of the system design process have a higher impact on the final result. Multiple supply voltage design is widely accepted as an effective way to reduce the power consumption of a CMOS circuit. A lower voltage design usually consumes less power butis also slower than a higher voltage design for the same logic block. Hence, the idea is to use the higher voltage blocks on the critical path components and lower voltage blocks on the non-critical path components under time and resource constraints, so that the total power dissipation canbe reduced and the system still meets the performance. A heuristic to explore the wider design space for more optimal designs using a SAT (satisfiability) based approach which targets operation scheduling at high level synthesis stage with varying voltages and produces a circuit which consumesless power has been proposed in this paper. The experiments with high level synthesis benchmarks shows that the proposed approach achieves a significant power reduction when the operating voltages are 5 V, 3.3 V and 2.4 V.
机译：系统设计过程最早阶段的功率降低对最终结果产生了更高的影响。多种电源电压设计被广泛接受为降低CMOS电路的功耗的有效方法。较低的电压设计通常消耗较少的功率，而不是相同逻辑块的更高电压设计慢。因此，该想法是在时间和资源约束下使用临界路径分量和较低电压块上的较高电压块，从而降低总功耗并且系统仍然符合性能。一种启发式，用于探索更广泛的设计空间，用于使用基于SAT（可满足性）的方法，该方法以不同的电压在高电平合成阶段的操作调度，并在本文中提出了无消耗功率的电路。具有高级合成基准测试的实验表明，当工作电压为5 V，3.3 V和2.4 V时，所提出的方法实现了显着的功率降低。

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