Fault and test-process modelling for integrated circuits

Juraj Povazanec; Vladislav Musil

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Fault and test-process modelling for integrated circuits

机译：集成电路故障和测试过程建模

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摘要

The paper is oriented to the modelling of test process of integrated circuits. It describes a usage of the wide possibilities of hspice and matlab to manage whole test simulation including the simulations of faulty or fault free circuits as well as post-processing of them. The simulation results are processed to obtain desired test values such as fault coverage or degree of detectability. Technique developed on math-package covers a wide spectrum of desired post-process techniques.

机译：本文面向集成电路测试过程的建模。它描述了利用HSPICE和MATLAB的广泛可能性，以管理整个测试仿真，包括故障或故障的仿真以及它们的后处理。处理模拟结果以获得所需的测试值，例如故障覆盖或可检测性程度。在数学包上开发的技术涵盖了广泛的期望后工艺技术。

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来源
《Journal of systems architecture》 |1997年第5期|共5页
作者
Juraj Povazanec; Vladislav Musil;
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作者单位

Leeds Metropolitan University Faculty of IES Calverley Street Leeds LS1 3HE United Kingdom;

Technical University of Brno Faculty of EECS Udolni 53 602 00 Brno Czech Republic;

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原文格式 PDF
正文语种 eng
中图分类计算技术、计算机技术;
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1. Fault and test-process modelling for integrated circuits [J] . Juraj Povazanec, Vladislav Musil Journal of systems architecture . 1997,第1a5期

机译：集成电路故障和测试过程建模
2. Accurate Conjunction of Yield Models for Fault-Tolerant Memory Integrated Circuits [J] . Chunghun Ha, Way Kuo, Jung Yoon Hwang Semiconductor Manufacturing, IEEE Transactions on . 2009,第3期

机译：容错存储集成电路的良率模型的精确联合
3. Yield model for fault clusters within integrated circuits [J] . IBM Journal of Research and Development . 1984,第5期

机译：集成电路内故障簇的产量模型
4. Modelling Thermally-Induced Mechanical Faults in Power Integrated Circuits Assemblies [C] . A. Bojiţă, M. Purcar, V. Ţopa, IEEE International Symposium for Design and Technology in Electronic Packaging . 2020

机译：电力集成电路组件中的热诱导机械故障建模
5. Automated diagnosis of path delay faults in digital integrated circuits. [D] . Pant, Pankaj. 2000

机译：自动诊断数字集成电路中的路径延迟故障。
6. Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip [O] . Danny Dolev, Matthias Függer, Markus Posch, -1

机译：严格建模自稳定的容错电路：片上系统的超鲁棒时钟方案
7. Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation [O] . Zhong Shida 2013

机译：工艺变化下集成电路制造缺陷的故障建模与加速仿真
8. Technique for Evaluating the Application of the Pin-Level Stuck-at Fault Model to VLSI (Very Large Scale Integrated) Circuits, [R] . palumbo, d. l. finelli, g. b. 1987

机译：针对超大规模集成电路的超高压集成电路应用引脚级卡住故障模型的评估技术，

Fault and test-process modelling for integrated circuits

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