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首页> 外文期刊>Journal of systems architecture >Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures
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Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures

机译：Prenaut：具有各种片上架构的嵌入式对称多处理的设计空间探索

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摘要

As embedded systems have evolved to appear in many different domains, symmetric multiprocessing (SMP) has been the design choice from low-end to high-end devices. In this paper we present Prenaut, a design space exploration method for finding the best on-chip SMP architectures given processor cores, Level 1, Level 2, and Level 3 caches. finlike traditional design space exploration tools that are majorly concerned with optimizations in processor, memory and cache structures with a fixed on-chip architecture, Prenaut explores architectures that have not been considered in symmetric multiprocessing domain. These architectures consist of shared instruction caches between cores and heterogeneous cache topologies that feature bypassing a level in the cache hierarchy. The design idea behind Prenaut is to build a data oriented design space exploration method that exploits simulation data to its full extent rather than discarding it. Therefore, Prenaut uses simulation data and applies machine learning methods for estimating design parameters. This provides very rapid estimation of the Pareto set and guides designers through the overall system design process. The design space is pruned by topological clustering of design points which groups similar topologies and new simulation points are selected via an ordered look up table that prevents infeasible random jumps in the design space. For the selected benchmarks, Prenaut can estimate the Pareto set up to 147x faster and the clustering information can reduce the design space up to 82% in comparison with a state-of-the-art evolutionary algorithm. (C) 2016 Elsevier B.V. All rights reserved.
机译：由于嵌入式系统进化出来出现在许多不同的域中，对称多处理（SMP）是从低端到高端设备的设计选择。在本文中，我们呈现Prenaut，一种设计空间探索方法，用于找到优化的片上SMP架构给定处理器核心，1级，2级和3级缓存。 Finlike传统设计空间探索工具主要关注处理器，内存和缓存结构中的优化，具有固定的片上架构，Prenaut探讨了在对称多处理域中未考虑的架构。这些体系结构包括核心和异构缓存拓扑之间的共享指令缓存，该拓扑拓扑结构在缓存层次结构中绕过级别。 Prenaut背后的设计理念是建立一个数据面向数据的设计空间探索方法，该方法将仿真数据充分利用到其全部，而不是丢弃它。因此，Prenaut使用仿真数据并应用用于估计设计参数的机器学习方法。这提供了通过整体系统设计过程的帕累托集和指导设计人员非常快速的估计。通过设计点的拓扑聚类来修剪设计空间，该设计点通过订购的查找表选择了类似拓扑和新的模拟点，这可以防止在设计空间中的不可行随机跳转。对于所选基准测试，Prenaut可以估计最多147倍的Pareto，并且聚类信息可以与最先进的进化算法相比，群集信息可以将高达82％的设计空间降低82％。 （c）2016年Elsevier B.v.保留所有权利。

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