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首页> 外文期刊>International Journal of Signal and Imaging Systems Engineering >Architectural design of a Radix-4 CORDIC-based Radix-4 IFFT algorithm and its FPGA implementation
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Architectural design of a Radix-4 CORDIC-based Radix-4 IFFT algorithm and its FPGA implementation

机译:基于Radix-4 CORDIC的Radix-4 IFFT算法的体系结构设计及其FPGA实现

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摘要

In high speed applications, it is wise to use Radix-4 algorithm, when the number of data points is the power of four, instead of using the conventional Radix-2 algorithm. In this paper a CORDIC based almost multiplier less architecture for a 16 point Radix-4 IFFT is presented. With the concurrent use of pipelining and parallelism, the advantages of minimisation of latency time and the increment of the throughput rate is achieved. The whole Radix-4 CORDIC-based Radix-4 IFFT architecture is implemented on an FPGA device with the accuracy up to 32-bit precision operating frequency at 55 MHz making it suitable for real-time applications.
机译:在高速应用中,明智的做法是使用Radix-4算法(当数据点数为4的幂时),而不是使用常规Radix-2算法。本文提出了一种基于CORDIC的几乎无乘法器的16点Radix-4 IFFT架构。通过同时使用流水线和并行性,可以实现延迟时间最小化和吞吐率提高的优点。整个基于Radix-4基于CORDIC的Radix-4 IFFT架构在FPGA器件上实现,在55 MHz时的精度高达32位精度工作频率,使其适合于实时应用。

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