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首页> 外文期刊>ECS Journal of Solid State Science and Technology >CMP-Less Planarizatioe Technology with SOG/LTO Etchback for Low-Cost HIgh-k/Metal Gate-Last Integration
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CMP-Less Planarizatioe Technology with SOG/LTO Etchback for Low-Cost HIgh-k/Metal Gate-Last Integration

机译：具有SOG / LTO刻蚀的CMP少平面技术，可实现低成本的高k /金属栅极-最后集成

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摘要

A novel CMP-less planarization technology featuring a SOG/LTO (Spin-on Glass /Low-Temperature Oxide) etchback method is presented to develop a high-performance, low-cost, high-k/metal gate-last (HK/MG-last) integration process. For a special PMD (Pre-Metal Dielectric) poly-open-planarization, a new recessed three-step RIE (Reactive-Ion Etching) etchback process is developed in one process chamber. This method may replace general CMP with certain slurry. An etch-parameter study shows that an increase in the reaction gas pressure changes the SOG etch profile from convex to concave. This profile is more useful for realizing pseudo-global planarization of the entire PMD structure. The within-the-wafer PMD thickness uniformity reaches 95%, 5 mm from the wafer edge. By controlling the etch-rate difference between the SOG and LTO, a micro-concave effect on a dummy gate is demonstrated and used as a better selective wet-etching dummy poly-Si gate in TMAH (Tetramethylammonium hydroxide). With this method, the HK/MG-last PMOSFETs exhibit good electrical characteristics as well as a similar variation trend to the planarization results.
机译：提出了一种采用SOG / LTO（旋涂玻璃/低温氧化物）回蚀方法的新颖的无CMP平面化技术，以开发高性能，低成本，高k /金属栅后栅极（HK / MG） -last）集成过程。对于特殊的PMD（金属前电介质）多开口平面化工艺，在一个处理室中开发了一种新的凹进三步RIE（反应离子蚀刻）回蚀工艺。该方法可以用某些浆料代替一般的CMP。蚀刻参数研究表明，反应气体压力的增加将SOG蚀刻轮廓从凸形更改为凹形。此配置文件对于实现整个PMD结构的伪全局平面化更为有用。晶圆内PMD厚度均匀性达到95％，距离晶圆边缘5毫米。通过控制SOG和LTO之间的蚀刻速率差异，证明了对虚设栅极的微凹效应，并将其用作TMAH（氢氧化四甲基铵）中更好的选择性湿法蚀刻虚设多晶硅栅极。使用这种方法，HK / MG-last PMOSFET具有良好的电特性，并且具有与平坦化结果相似的变化趋势。

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