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首页> 外文期刊>ECS Journal of Solid State Science and Technology >Effect of Electrons Trapping/De-Trapping at Si-SiO_2 Interface on Two-State Current in MOS(p) Structure with Ultra-Thin SiO_2 by Anodization
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Effect of Electrons Trapping/De-Trapping at Si-SiO_2 Interface on Two-State Current in MOS(p) Structure with Ultra-Thin SiO_2 by Anodization

机译：Si-SiO_2界面电子俘获/去俘获对阳极氧化超薄SiO_2 MOS（p）结构中二态电流的影响

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摘要

The phenomenon of two-state inversion gate current of metal-oxide-semiconductor device with p-type substrate (Al/SiO_2/p-Si structure using an anodized SiO_2 layer) at V_G>0 was investigated. Different amounts of electrons are trapped/de-trapped at Si-SiO_2 interface after exerting different set/reset stressing voltages over different set/reset time. And the electron trapping/de-trapping at the Si-SiO_2 interface near the conduction band is thus proposed to rationalize the decreased/revertible gate current (I_(set) /I_(reset)) at Vq>0. In particular, the Iset increases with the decreasing amount of trapped electrons. Furthermore, a specific voltage of sustainable voltage is proposed to investigate the filling condition of the Si-SiO_2 interface traps in this paper. This simple and fully complementary metal-oxide-semiconductor compatible structure might have the potential application in memory devices.
机译：研究了具有p型衬底（采用阳极氧化SiO_2层的Al / SiO_2 / p-Si结构）的p型衬底的金属氧化物半导体器件在V_G> 0时的二态反转栅极电流的现象。在不同的置位/重置时间上施加不同的置位/重置应力后，会在Si-SiO_2界面上捕获/释放出不同数量的电子。因此，建议在导带附近的Si-SiO_2界面处进行电子俘获/去俘获，以合理化Vq> 0时减小/可恢复的栅极电流（I_（set）/ I_（reset））。特别是，Iset随着捕获电子数量的减少而增加。此外，提出了一种可持续电压的特定电压，以研究Si-SiO_2界面陷阱的填充条件。这种简单且完全互补的金属氧化物半导体兼容结构可能在存储设备中具有潜在的应用。

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