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首页> 外文期刊>ECS Journal of Solid State Science and Technology >Reduction in the Interfacial Trap Density of Al_2O_3/GaAs Gate Stack by Adopting High Pressure Oxidation
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Reduction in the Interfacial Trap Density of Al_2O_3/GaAs Gate Stack by Adopting High Pressure Oxidation

机译：采用高压氧化降低Al_2O_3 / GaAs栅叠层的界面陷阱密度

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摘要

The high interfacial trap density in GaAs MOS capacitors is one of the critical issues for realizing high mobility field-effect transistors. This paper proposes a new approach involving the high pressure thermal oxidation (HPO) of GaAs and subsequent HF etching prior to the deposition of an Al_2O_3 dielectric film. The HPO-treated MOS capacitors exhibited better electrical properties, such as reduced hysteresis and frequency dispersion compared to those of the control capacitors. These improvements were attributed to their reduced interfacial trap density. The relevant rationale is discussed based on the suppression of the Ga_2O_3 layer between the Al_2O_3 dielectric and GaAs semiconductor, which resulted from the As excess and Ga deficient surface modification via HPO and subsequent HF etching.
机译：GaAs MOS电容器中的高界面陷阱密度是实现高迁移率场效应晶体管的关键问题之一。本文提出了一种新方法，该方法涉及在沉积Al_2O_3介电膜之前进行GaAs的高压热氧化（HPO）和随后的HF蚀刻。与控制电容器相比，经HPO处理的MOS电容器具有更好的电性能，例如减少了磁滞和频率色散。这些改进归因于它们降低的界面陷阱密度。基于抑制Al_2O_3介电层和GaAs半导体之间的Ga_2O_3层，讨论了相关的基本原理，这是由于通过HPO进行的As过量和Ga不足的表面改性以及随后的HF蚀刻导致的。

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