A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

Park J.-G.; Kim S.-J.; Shin M.-H.; Song S.-H.; Chung S.-W.; Enomoto H.; Shim T.-H.

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A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

机译：在纳米级绝缘体上应变硅上制造的多级无电容器存储单元

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A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ～ 1.7 times that with an unstrained silicon channel. This thereby enables both front-and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1ms retention time and 12νA memory margin. This is a step toward achieving a terabit volatile memory cell

机译：在绝缘体（FD sSOI n-MOSFET）的纳米级应变硅沟道上，使用完全耗尽的n-金属氧化物半导体场效应晶体管制造了多级无电容器存储单元。 FD sSOI n-MOSFET的硅沟道中0.73％的双轴拉伸应变将有效电子迁移率提高到无应变硅沟道的1.7倍。因此，这可以实现前栅极和后栅极单元操作，从而以1ms的保留时间和12μA的存储裕度演示了八级易失性存储单元操作。这是朝着实现太比特易失性存储单元迈进的一步

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《Nanotechnology》 |2011年第31期|共7页
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Park J.-G.; Kim S.-J.; Shin M.-H.; Song S.-H.; Chung S.-W.; Enomoto H.; Shim T.-H.;
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1. A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator [J] . Park J.-G., Kim S.-J., Shin M.-H., Nanotechnology . 2011,第31期

机译：在纳米级绝缘体上应变硅上制造的多级无电容器存储单元
2. Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator [J] . Seong-Je Kim, Jung-Mi Oh, Tae-Hun Shim, Japanese journal of applied physics . 2010,第3issue1期

机译：在完全耗尽的绝缘体上硅上制造的电容器少用存储单元的高存储余量的最佳沟道离子注入
3. Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator [J] . Seong-Je Kim Tae-Hyun Kim Tae-Hun Shim and Jea-Gun Park Aplied Physics Letteres . 2010,第16期

机译：在绝缘体上应变硅锗层上的纳米级无应变硅层上制造的无电容器存储单元
4. Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer [C] . An Ho-Myoung, Kim Kyong Heon, Kim Hee-Dong, 2012 IEEE Silicon Nanoelectronics Workshop . 2012

机译：在Si3N4俘获层上以纳米级图案制造的电荷俘获闪存器件
5. Architectural techniques for multi-level cell phase change memory based main memory. [D] . Jiang, Lei. 2014

机译：基于多级单元相变存储器的主存储器的架构技术。
6. Transparent Multi-level Resistive Switching Phenomena Observed in ITO/RGO/ITO Memory Cells by the Sol-Gel Dip-Coating Method [O] . Hee-Dong Kim, Min Ju Yun, Jae Hoon Lee, -1

机译：溶胶/凝胶浸涂法在ITO / RGO / ITO存储单元中观察到透明的多级电阻切换现象
7. Fully tensile strained partial silicon-on-insulator n-type lateral-double-diffused metal-oxide-semiconductor field effect transistor using localized contact etching stop layers [O] . Xiangzhan Wang, Changgui Tan, Xi Zou, 2017

机译：完全拉伸的应变部分硅绝缘体n型采用局域化的横向双扩散金属氧化物半导体场效应晶体管接触蚀刻停止层

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

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