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首页> 外文期刊>Japanese journal of applied physics >Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator
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Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator

机译：在完全耗尽的绝缘体上硅上制造的电容器少用存储单元的高存储余量的最佳沟道离子注入

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摘要

The effect of channel doping concentration on the memory margin of capacitor-less (Cap-less) memory cells fabricated on fully depleted silicon-on-insulator (SOI) n-metal-oxide-semiconductor field-effect transistors (MOSFETs) was investigated. It was observed that the memory margin of Cap-less memory cells is significantly varied by the channel doping concentration, i.e., it increases with doping concentrations up to 1.4 × 10~（17）cm~(-3) and then decreases with higher doping concentrations. In particular, at a concentration of 1.4 × 10~(17)cm~(-3) it increased 1.8 times compared with that at 1.5 × 10~(15)cm~(-3). This gives rise to speculation that the memory margin of Cap-less memory cells fabricated on fully depleted SOI n-MOSFETs can be increased by enlarging the lateral electric field and can be decreased by reducing the current density. These results suggest that a higher memory margin in Cap-less memory cells can be obtained by optimizing channel doping concentration in fully depleted SOI n-MOSFETs.
机译：研究了沟道掺杂浓度对在完全耗尽的绝缘体上硅（SOI）n-金属氧化物半导体场效应晶体管（MOSFET）上制造的无电容器（无帽）存储单元的存储裕度的影响。观察到，无帽存储单元的存储裕度随沟道掺杂浓度而显着变化，即，随着掺杂浓度高达1.4×10〜（17）cm〜（-3）的增加，存储容限的增加浓度。特别是在浓度为1.4×10〜（17）cm〜（-3）的情况下，其浓度是1.5×10〜（15）cm〜（-3）的1.8倍。这引起了这样的推测：在完全耗尽的SOI n-MOSFET上制造的无电容存储单元的存储裕度可以通过增大横向电场来增加，而可以通过减小电流密度来减小。这些结果表明，可以通过优化完全耗尽的SOI n-MOSFET中的沟道掺杂浓度来获得无电容存储单元中更高的存储裕度。

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  • 来源
    《Japanese journal of applied physics》 |2010年第3issue1期|p.036507.1-036507.4|共4页
  • 作者

    Seong-Je Kim; Jung-Mi Oh; Tae-Hun Shim; Jea-Gun Park;

  • 作者单位

    Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea;

    Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea;

    Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea;

    Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea;

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