This work describes the modelling of a planar integrated inductor on silicon. In this case modelling means that we try to build a subcircuit model for circuit design purposes. The goal of the model is that all its elements could be derived from process parameters and layout geometrics rather than measured performance. This model has been programmed to operate as a defined model component of the APLAC circuit simulator, and it is optimized for integrated inductors having non-tapered, squared and full turns. Matching of the developed model with measured results is very good a wide range of inductance, but the model needs still four parameters to be determined empirically from process test structures. [References: 3]
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