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首页> 外文期刊>Physica status solidi, B. Basic research >Alternative techniques to reduce interface traps in n-type 4H-SiC MOS capacitors
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Alternative techniques to reduce interface traps in n-type 4H-SiC MOS capacitors

机译：减少n型4H-SiC MOS电容器中的界面陷阱的替代技术

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Several alternative oxidation techniques are developed and tested with the aim to reduce the high density of interface traps D-it in n-type 4H-SiC MOS capacitors. A lamp furnace in combination with a microwave plasma is employed to grow thin oxide layers, which are used for an insulating stack (SiO2 and Al2O3). The treatment of the oxide with nitrogen is another way to lower Dit. We introduce N atoms prior to the oxidation by ion implantation. During the oxidation process, the implanted N-profile is redistributed; a considerable amount of the implanted N is accumulated at the SiC/SiO2-interface, which leads to a strong reduction of D-it and a large negative flatband voltage. The negative flatband voltage can largely be compensated by coimplantation of aluminum. A model is proposed, which explains the passivation of interface traps in n-type 4H-SiC MOS capacitors. (C) 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
机译：为了减少n型4H-SiC MOS电容器中界面陷阱D-it的高密度，已开发并测试了多种替代氧化技术。结合微波等离子体的灯炉用于生长薄的氧化物层，该氧化物层用于绝缘叠层（SiO2和Al2O3）。用氮处理氧化物是降低Dit的另一种方法。在通过离子注入进行氧化之前，我们先引入N个原子。在氧化过程中，注入的N型轮廓会重新分布;大量的注入的N积累在SiC / SiO2界面处，这导致D-it的强烈降低和较大的负平带电压。负平坦带电压可以通过共注入铝来补偿。提出了一个模型，该模型解释了n型4H-SiC MOS电容器中界面陷阱的钝化。 （C）2008 WILEY-VCH Verlag GmbH＆Co. KGaA，Weinheim。

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