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大規模システムLSI設計のための統一的ハードウェア・ソフトウェア協調検証手法

机译：大规模系统LSI设计的统一软硬件协同验证方法

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摘要

Currently, the complexity of embedded LSI system is growing faster than the productivity of system design. This trend results in a design productivity gap, particularly in tight development time. Since the verification task takes bigger part of development task, it becomes a major challenge in LSI system design. In order to guarantee system reliability and quality of results (QoR), verifying large coverage of system functionality requires huge amount of relevant test cases and various scenario of evaluations. To overcome these problems, verification methodology is evolving toward supporting higher level of design abstraction by employing HW-SW co-verification. In this study, we present a novel approach for verification LSI circuit which is called as unified HW/SW co-verification framework. The study aims to improve design efficiency while maintains implementation consistency in the point of view of system-level performance. The proposed data-driven simulation and flexible interface of HW and SW design become the backbone of verification framework. In order to avoid time consuming, prone error, and iterative design spin-off in a large team, the proposed framework has to support multiple design abstractions. Hence, it can close the loop of design, exploration, optimization, and testing. Furthermore, the proposed methodology is also able to co-operate with system-level simulation in high-level abstraction, which is easy to extend for various applications and enables fast-turn around design modification. These contributions are discussed in chapter 3. In order to show the effectiveness and the use-cases of the proposed verification framework, the evaluation and metrics assessments of Very High Throughput wireless LAN system design are carried out. Two application examples are provided. The first case in chapter 4 is intended for fast verification and design exploration of large circuit. The Maximum Likelihood Detection (MLD) MIMO decoder is considered as Design Under Test (DUT). The second case, as presented in chapter 5, is the evaluation for system-level simulation. The full transceiver system based on IEEE 802.11ac standard is employed as DUT. Experimental results show that the proposed verification approach gives significant improvements of verification time (e.g. up to 10,000 times) over the conventional scheme. The proposed framework is also able to support various schemes of system level evaluations and cross-layer evaluation of wireless system.
机译：当前，嵌入式LSI系统的复杂性增长速度超过了系统设计的生产率。这种趋势导致设计生产率的差距，特别是紧迫的开发时间。由于验证任务占开发任务的大部分，因此它成为LSI系统设计中的主要挑战。为了保证系统的可靠性和结果质量（QoR），验证系统功能的大范围覆盖需要大量相关的测试用例和各种评估方案。为了克服这些问题，验证方法正朝着通过采用硬件-软件协同验证支持更高级别的设计抽象的方向发展。在这项研究中，我们提出了一种用于验证LSI电路的新颖方法，称为统一的硬件/软件共验证框架。该研究旨在提高设计效率，同时从系统级性能的角度保持实现的一致性。所提出的硬件和软件设计的数据驱动仿真和灵活的接口成为验证框架的骨干。为了避免在大型团队中浪费时间，容易出错和迭代设计衍生出来，所提出的框架必须支持多个设计抽象。因此，它可以关闭设计，探索，优化和测试的循环。此外，所提出的方法还能够与高级抽象中的系统级仿真配合使用，这很容易扩展到各种应用程序，并能够快速完成设计修改。这些贡献将在第3章中进行讨论。为了显示所提出的验证框架的有效性和用例，我们对甚高吞吐量无线LAN系统设计进行了评估和指标评估。提供了两个应用示例。第4章中的第一种情况旨在用于大型电路的快速验证和设计探索。最大似然检测（MLD）MIMO解码器被认为是被测设计（DUT）。如第5章所述，第二种情况是对系统级仿真的评估。基于IEEE 802.11ac标准的完整收发器系统用作DUT。实验结果表明，与传统方案相比，所提出的验证方法可显着改善验证时间（例如，最多10,000次）。所提出的框架还能够支持无线系统的系统级评估和跨层评估的各种方案。

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    Nana Sutisna;

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  • 年度 2017
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