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HIGH QUALITY PHYSICAL DESIGN FOR MONOLITHIC THREE-DIMENSIONAL INTEGRATED CIRCUITS (3D IC) USING TWO-DIMENSIONAL INTEGRATED CIRCUIT (2D IC) DESIGN TOOLS
HIGH QUALITY PHYSICAL DESIGN FOR MONOLITHIC THREE-DIMENSIONAL INTEGRATED CIRCUITS (3D IC) USING TWO-DIMENSIONAL INTEGRATED CIRCUIT (2D IC) DESIGN TOOLS
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机译：使用二维集成电路（2D IC）设计工具对全尺寸三维集成电路（3D IC）进行高质量的物理设计
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摘要
A method of designing a multi-tier three-dimensional integrated circuit (3D IC) is provided that allows the use of two-dimensional integrated circuit (2D IC) design tools. When a 2D IC design tool is used, a macro for each of the tiers indicating areas available and unavailable for placement of circuit elements in each tier is created, and the macros are superimposed on one another. Circuit elements to be implemented in the 3D IC, such as logic cells and interconnects, are shrunk and then placed and repopulated on the superimposed macro. The repopulated circuit elements on the superimposed macro are then partitioned into tiers. Monolithic inter-tier via (MIV) placement and tier-to-tier routing are designed to provide electrical connections between circuit elements in different tiers. Power, performance and area (PPA) optimization may also be performed to optimize the 3D IC layout.
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